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https://github.com/projectacrn/acrn-hypervisor.git
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cd40980d5f
change the input parameter from vcpu to eptp in order to let this api more generic, no need to care normal world or secure world. Tracked-On: #1842 Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
286 lines
6.1 KiB
C
286 lines
6.1 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file pgtable.h
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*
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* @brief Address translation and page table operations
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*/
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#ifndef PGTABLE_H
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#define PGTABLE_H
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#include <page.h>
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#define PAGE_PRESENT (1UL << 0U)
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#define PAGE_RW (1UL << 1U)
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#define PAGE_USER (1UL << 2U)
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#define PAGE_PWT (1UL << 3U)
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#define PAGE_PCD (1UL << 4U)
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#define PAGE_ACCESSED (1UL << 5U)
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#define PAGE_DIRTY (1UL << 6U)
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#define PAGE_PSE (1UL << 7U)
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#define PAGE_GLOBAL (1UL << 8U)
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#define PAGE_PAT_LARGE (1UL << 12U)
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#define PAGE_NX (1UL << 63U)
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#define PAGE_CACHE_MASK (PAGE_PCD | PAGE_PWT)
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#define PAGE_CACHE_WB 0UL
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#define PAGE_CACHE_WT PAGE_PWT
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#define PAGE_CACHE_UC_MINUS PAGE_PCD
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#define PAGE_CACHE_UC (PAGE_PCD | PAGE_PWT)
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/**
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* @defgroup ept_mem_access_right EPT Memory Access Right
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*
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* This is a group that includes EPT Memory Access Right Definitions.
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*
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* @{
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*/
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/**
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* @brief EPT memory access right is read-only.
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*/
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#define EPT_RD (1UL << 0U)
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/**
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* @brief EPT memory access right is read/write.
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*/
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#define EPT_WR (1UL << 1U)
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/**
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* @brief EPT memory access right is executable.
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*/
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#define EPT_EXE (1UL << 2U)
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/**
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* @brief EPT memory access right is read/write and executable.
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*/
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#define EPT_RWX (EPT_RD | EPT_WR | EPT_EXE)
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/**
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* @}
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*/
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/* End of ept_mem_access_right */
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/**
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* @defgroup ept_mem_type EPT Memory Type
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*
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* This is a group that includes EPT Memory Type Definitions.
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*
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* @{
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*/
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/**
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* @brief EPT memory type is specified in bits 5:3 of the EPT paging-structure entry.
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*/
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#define EPT_MT_SHIFT 3U
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/**
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* @brief EPT memory type is uncacheable.
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*/
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#define EPT_UNCACHED (0UL << EPT_MT_SHIFT)
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/**
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* @brief EPT memory type is write combining.
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*/
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#define EPT_WC (1UL << EPT_MT_SHIFT)
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/**
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* @brief EPT memory type is write through.
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*/
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#define EPT_WT (4UL << EPT_MT_SHIFT)
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/**
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* @brief EPT memory type is write protected.
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*/
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#define EPT_WP (5UL << EPT_MT_SHIFT)
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/**
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* @brief EPT memory type is write back.
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*/
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#define EPT_WB (6UL << EPT_MT_SHIFT)
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/**
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* @}
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*/
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/* End of ept_mem_type */
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#define EPT_MT_MASK (7UL << EPT_MT_SHIFT)
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/* VTD: Second-Level Paging Entries: Snoop Control */
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#define EPT_SNOOP_CTRL (1UL << 11U)
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#define EPT_VE (1UL << 63U)
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/* EPT leaf entry bits (bit 52 - bit 63) should be maksed when calculate PFN */
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#define EPT_PFN_HIGH_MASK 0xFFF0000000000000UL
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#define PML4E_SHIFT 39U
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#define PTRS_PER_PML4E 512UL
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#define PML4E_SIZE (1UL << PML4E_SHIFT)
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#define PML4E_MASK (~(PML4E_SIZE - 1UL))
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#define PDPTE_SHIFT 30U
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#define PTRS_PER_PDPTE 512UL
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#define PDPTE_SIZE (1UL << PDPTE_SHIFT)
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#define PDPTE_MASK (~(PDPTE_SIZE - 1UL))
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#define PDE_SHIFT 21U
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#define PTRS_PER_PDE 512UL
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#define PDE_SIZE (1UL << PDE_SHIFT)
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#define PDE_MASK (~(PDE_SIZE - 1UL))
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#define PTE_SHIFT 12U
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#define PTRS_PER_PTE 512UL
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#define PTE_SIZE (1UL << PTE_SHIFT)
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#define PTE_MASK (~(PTE_SIZE - 1UL))
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/* TODO: PAGE_MASK & PHYSICAL_MASK */
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#define PML4E_PFN_MASK 0x0000FFFFFFFFF000UL
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#define PDPTE_PFN_MASK 0x0000FFFFFFFFF000UL
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#define PDE_PFN_MASK 0x0000FFFFFFFFF000UL
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/**
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* @brief Address space translation
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*
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* @addtogroup acrn_mem ACRN Memory Management
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* @{
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*/
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/* hpa <--> hva, now it is 1:1 mapping */
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/**
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* @brief Translate host-physical address to host-virtual address
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*
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* @param[in] x The specified host-physical address
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*
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* @return The translated host-virtual address
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*/
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static inline void *hpa2hva_early(uint64_t x)
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{
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return (void *)x;
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}
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/**
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* @brief Translate host-virtual address to host-physical address
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*
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* @param[in] x The specified host-virtual address
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*
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* @return The translated host-physical address
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*/
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static inline uint64_t hva2hpa_early(void *x)
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{
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return (uint64_t)x;
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}
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/**
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* @brief Translate host-physical address to host-virtual address
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*
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* @param[in] x The specified host-physical address
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*
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* @return The translated host-virtual address
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*/
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static inline void *hpa2hva(uint64_t x)
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{
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return (void *)x;
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}
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/**
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* @brief Translate host-virtual address to host-physical address
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*
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* @param[in] x The specified host-virtual address
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*
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* @return The translated host-physical address
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*/
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static inline uint64_t hva2hpa(const void *x)
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{
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return (uint64_t)x;
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}
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static inline uint64_t pml4e_index(uint64_t address)
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{
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return (address >> PML4E_SHIFT) & (PTRS_PER_PML4E - 1UL);
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}
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static inline uint64_t pdpte_index(uint64_t address)
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{
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return (address >> PDPTE_SHIFT) & (PTRS_PER_PDPTE - 1UL);
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}
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static inline uint64_t pde_index(uint64_t address)
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{
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return (address >> PDE_SHIFT) & (PTRS_PER_PDE - 1UL);
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}
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static inline uint64_t pte_index(uint64_t address)
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{
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return (address >> PTE_SHIFT) & (PTRS_PER_PTE - 1UL);
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}
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static inline uint64_t *pml4e_page_vaddr(uint64_t pml4e)
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{
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return hpa2hva(pml4e & PML4E_PFN_MASK);
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}
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static inline uint64_t *pdpte_page_vaddr(uint64_t pdpte)
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{
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return hpa2hva(pdpte & PDPTE_PFN_MASK);
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}
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static inline uint64_t *pde_page_vaddr(uint64_t pde)
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{
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return hpa2hva(pde & PDE_PFN_MASK);
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}
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static inline uint64_t *pml4e_offset(uint64_t *pml4_page, uint64_t addr)
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{
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return pml4_page + pml4e_index(addr);
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}
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static inline uint64_t *pdpte_offset(const uint64_t *pml4e, uint64_t addr)
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{
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return pml4e_page_vaddr(*pml4e) + pdpte_index(addr);
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}
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static inline uint64_t *pde_offset(const uint64_t *pdpte, uint64_t addr)
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{
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return pdpte_page_vaddr(*pdpte) + pde_index(addr);
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}
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static inline uint64_t *pte_offset(const uint64_t *pde, uint64_t addr)
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{
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return pde_page_vaddr(*pde) + pte_index(addr);
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}
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/*
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* pgentry may means pml4e/pdpte/pde/pte
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*/
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static inline uint64_t get_pgentry(const uint64_t *pte)
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{
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return *pte;
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}
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/*
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* pgentry may means pml4e/pdpte/pde/pte
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*/
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static inline void set_pgentry(uint64_t *ptep, uint64_t pte, const struct memory_ops *mem_ops)
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{
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*ptep = pte;
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mem_ops->clflush_pagewalk(ptep);
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}
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static inline uint64_t pde_large(uint64_t pde)
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{
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return pde & PAGE_PSE;
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}
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static inline uint64_t pdpte_large(uint64_t pdpte)
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{
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return pdpte & PAGE_PSE;
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}
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/**
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*@pre (pml4_page != NULL) && (pg_size != NULL)
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*/
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const uint64_t *lookup_address(uint64_t *pml4_page, uint64_t addr,
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uint64_t *pg_size, const struct memory_ops *mem_ops);
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/**
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* @}
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*/
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#endif /* PGTABLE_H */
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