mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-05 15:06:58 +00:00
88cf1229a7
After upgrading to guest kernel 6.1.80, it checks the CPPC V2 capability in _OSC of DSDT. To support it for ACRN guest, add CPPC V2 capability in _OSC of DSDT. Currently we only support CPPC V2 capability in _OSC of DSDT. Tracked-On: #8691 Signed-off-by: Yuan Lu <yuan.y.lu@intel.com> Reviewed-by: Fei Li <fei1.li@intel.com>
492 lines
13 KiB
C
492 lines
13 KiB
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <stdbool.h>
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#include "vmmapi.h"
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#include "acpi.h"
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static inline int get_vcpu_pm_info(struct vmctx *ctx, int vcpu_id,
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uint64_t pm_type, uint64_t *pm_info)
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{
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*pm_info = ((ctx->vmid << PMCMD_VMID_SHIFT) & PMCMD_VMID_MASK)
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| ((vcpu_id << PMCMD_VCPUID_SHIFT) & PMCMD_VCPUID_MASK)
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| (pm_type & PMCMD_TYPE_MASK);
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return vm_get_cpu_state(ctx, pm_info);
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}
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static inline int get_vcpu_px_cnt(struct vmctx *ctx, int vcpu_id, uint8_t *px_cnt)
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{
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uint64_t px_cnt_u64;
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int ret;
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ret = get_vcpu_pm_info(ctx, vcpu_id, ACRN_PMCMD_GET_PX_CNT, &px_cnt_u64);
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*px_cnt = (uint8_t)px_cnt_u64;
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return ret;
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}
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uint8_t get_vcpu_cx_cnt(struct vmctx *ctx, int vcpu_id)
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{
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uint64_t cx_cnt;
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if (get_vcpu_pm_info(ctx, vcpu_id, ACRN_PMCMD_GET_CX_CNT, &cx_cnt)) {
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return 0;
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}
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return (uint8_t)cx_cnt;
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}
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static int get_vcpu_px_data(struct vmctx *ctx, int vcpu_id,
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int px_num, struct acrn_pstate_data *vcpu_px_data)
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{
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uint64_t *pm_ioctl_buf;
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enum acrn_pm_cmd_type cmd_type = ACRN_PMCMD_GET_PX_DATA;
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pm_ioctl_buf = malloc(sizeof(struct acrn_pstate_data));
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if (!pm_ioctl_buf) {
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return -1;
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}
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*pm_ioctl_buf = ((ctx->vmid << PMCMD_VMID_SHIFT) & PMCMD_VMID_MASK)
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| ((vcpu_id << PMCMD_VCPUID_SHIFT) & PMCMD_VCPUID_MASK)
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| ((px_num << PMCMD_STATE_NUM_SHIFT) & PMCMD_STATE_NUM_MASK)
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| cmd_type;
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/* get and validate px data */
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if (vm_get_cpu_state(ctx, pm_ioctl_buf)) {
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free(pm_ioctl_buf);
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return -1;
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}
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memcpy(vcpu_px_data, pm_ioctl_buf,
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sizeof(struct acrn_pstate_data));
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free(pm_ioctl_buf);
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return 0;
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}
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int get_vcpu_cx_data(struct vmctx *ctx, int vcpu_id,
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int cx_num, struct acrn_cstate_data *vcpu_cx_data)
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{
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uint64_t *pm_ioctl_buf;
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enum acrn_pm_cmd_type cmd_type = ACRN_PMCMD_GET_CX_DATA;
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pm_ioctl_buf = malloc(sizeof(struct acrn_cstate_data));
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if (!pm_ioctl_buf) {
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return -1;
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}
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*pm_ioctl_buf = ((ctx->vmid << PMCMD_VMID_SHIFT) & PMCMD_VMID_MASK)
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| ((vcpu_id << PMCMD_VCPUID_SHIFT) & PMCMD_VCPUID_MASK)
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| ((cx_num << PMCMD_STATE_NUM_SHIFT) & PMCMD_STATE_NUM_MASK)
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| cmd_type;
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/* get and validate cx data */
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if (vm_get_cpu_state(ctx, pm_ioctl_buf)) {
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free(pm_ioctl_buf);
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return -1;
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}
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memcpy(vcpu_cx_data, pm_ioctl_buf,
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sizeof(struct acrn_cstate_data));
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free(pm_ioctl_buf);
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return 0;
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}
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char *_asi_table[7] = { "SystemMemory",
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"SystemIO",
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"PCI_Config",
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"EmbeddedControl",
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"SMBus",
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"PCC",
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"FFixedHW"};
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static char *get_asi_string(uint8_t space_id)
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{
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switch (space_id) {
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case SPACE_SYSTEM_MEMORY:
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return _asi_table[0];
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case SPACE_SYSTEM_IO:
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return _asi_table[1];
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case SPACE_PCI_CONFIG:
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return _asi_table[2];
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case SPACE_Embedded_Control:
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return _asi_table[3];
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case SPACE_SMBUS:
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return _asi_table[4];
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case SPACE_PLATFORM_COMM:
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return _asi_table[5];
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case SPACE_FFixedHW:
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return _asi_table[6];
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default:
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return NULL;
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}
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}
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/* _CST: C-States
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*/
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void dsdt_write_cst(struct vmctx *ctx, int vcpu_id)
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{
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int i;
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uint8_t vcpu_cx_cnt;
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char *cx_asi;
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struct acrn_acpi_generic_address cx_reg;
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struct acrn_cstate_data *vcpu_cx_data;
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vcpu_cx_cnt = get_vcpu_cx_cnt(ctx, vcpu_id);
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if (!vcpu_cx_cnt) {
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return;
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}
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/* vcpu_cx_data start from C1, cx_cnt is total Cx entry num. */
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vcpu_cx_data = malloc(vcpu_cx_cnt * sizeof(struct acrn_cstate_data));
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if (!vcpu_cx_data) {
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return;
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}
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/* copy and validate cx data first */
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for (i = 1; i <= vcpu_cx_cnt; i++) {
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if (get_vcpu_cx_data(ctx, vcpu_id, i, vcpu_cx_data + i - 1)) {
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/* something must be wrong, so skip the write. */
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free(vcpu_cx_data);
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return;
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}
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}
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dsdt_line("");
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dsdt_line(" Method (_CST, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (Package (0x%02X)", vcpu_cx_cnt + 1);
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dsdt_line(" {");
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dsdt_line(" 0x%02X,", vcpu_cx_cnt);
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for (i = 0; i < vcpu_cx_cnt; i++) {
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dsdt_line(" Package (0x04)");
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dsdt_line(" {");
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cx_reg = (vcpu_cx_data + i)->cx_reg;
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cx_asi = get_asi_string(cx_reg.space_id);
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dsdt_line(" ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_line(" Register (%s,", cx_asi);
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dsdt_line(" 0x%02x,", cx_reg.bit_width);
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dsdt_line(" 0x%02x,", cx_reg.bit_offset);
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dsdt_line(" 0x%016lx,", cx_reg.address);
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dsdt_line(" 0x%02x,", cx_reg.access_size);
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dsdt_line(" )");
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dsdt_line(" },");
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dsdt_line(" 0x%04X,", (vcpu_cx_data + i)->type);
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dsdt_line(" 0x%04X,", (vcpu_cx_data + i)->latency);
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dsdt_line(" 0x%04X", (vcpu_cx_data + i)->power);
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if (i == (vcpu_cx_cnt - 1)) {
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dsdt_line(" }");
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} else {
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dsdt_line(" },");
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}
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}
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dsdt_line(" })");
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dsdt_line(" }");
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free(vcpu_cx_data);
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}
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/* _PPC: Performance Present Capabilities
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* hard code _PPC to 0, all states are available.
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*/
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static void dsdt_write_ppc(void)
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{
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dsdt_line(" Name (_PPC, Zero)");
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}
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/* _PCT: Performance Control
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* Both Performance Control and Status Register are set to FFixedHW
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*/
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static void dsdt_write_pct(void)
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{
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dsdt_line(" Method (_PCT, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (Package (0x02)");
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dsdt_line(" {");
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dsdt_line(" ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_line(" Register (FFixedHW,");
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dsdt_line(" 0x00,");
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dsdt_line(" 0x00,");
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dsdt_line(" 0x0000000000000000,");
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dsdt_line(" ,)");
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dsdt_line(" },");
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dsdt_line("");
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dsdt_line(" ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_line(" Register (FFixedHW,");
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dsdt_line(" 0x00,");
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dsdt_line(" 0x00,");
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dsdt_line(" 0x0000000000000000,");
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dsdt_line(" ,)");
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dsdt_line(" }");
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dsdt_line(" })");
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dsdt_line(" }");
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}
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/* _PSS: Performance Supported States
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*/
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static int dsdt_write_pss(struct vmctx *ctx, int vcpu_id)
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{
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uint8_t vcpu_px_cnt;
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int i;
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struct acrn_pstate_data *vcpu_px_data;
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int ret;
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ret = get_vcpu_px_cnt(ctx, vcpu_id, &vcpu_px_cnt);
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/* vcpu_px_cnt = 0 Indicates vcpu supports continuous pstate.
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* Then we should write _CPC instate of _PSS
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*/
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if (ret || !vcpu_px_cnt) {
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return -1;
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}
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vcpu_px_data = malloc(vcpu_px_cnt * sizeof(struct acrn_pstate_data));
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if (!vcpu_px_data) {
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return -1;
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}
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/* copy and validate px data first */
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for (i = 0; i < vcpu_px_cnt; i++) {
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if (get_vcpu_px_data(ctx, vcpu_id, i, vcpu_px_data + i)) {
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/* something must be wrong, so skip the write. */
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free(vcpu_px_data);
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return -1;
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}
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}
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dsdt_line("");
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dsdt_line(" Method (_PSS, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (Package (0x%02X)", vcpu_px_cnt);
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dsdt_line(" {");
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for (i = 0; i < vcpu_px_cnt; i++) {
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dsdt_line(" Package (0x%02X)", 6);
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dsdt_line(" {");
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->core_frequency);
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->power);
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->transition_latency);
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->bus_master_latency);
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->control);
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dsdt_line(" 0x%08X",
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(vcpu_px_data + i)->status);
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if (i == (vcpu_px_cnt - 1)) {
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dsdt_line(" }");
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} else {
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dsdt_line(" },");
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}
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}
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dsdt_line(" })");
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dsdt_line(" }");
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free(vcpu_px_data);
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return 0;
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}
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/* _CPC: Continuous Performance Control
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* Hard code a V3 CPC table, describing HWP register interface.
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*/
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static void dsdt_write_cpc(void)
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{
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dsdt_line("");
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dsdt_line(" Method (_CPC, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (Package (0x17)");
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dsdt_line(" {");
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dsdt_line(" 0x17,");
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dsdt_line(" 0x03,");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x00, 0x0000000000000771, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x00000000000000CE, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x10, 0x0000000000000771, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x18, 0x0000000000000771, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x0000000000000771, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x10, 0x0000000000000774, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x00, 0x0000000000000774, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x08, 0x0000000000000774, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
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dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
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dsdt_line(" ResourceTemplate() {Register(SystemMemory, 0x00, 0x00, 0x0000000000000000, , )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40, 0x00, 0x00000000000000E7, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x40, 0x00, 0x00000000000000E8, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x02, 0x01, 0x0000000000000777, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x01, 0x00, 0x0000000000000770, 0x04, )},");
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dsdt_line(" One,");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x0A, 0x20, 0x0000000000000774, 0x04, )},");
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dsdt_line(" ResourceTemplate() {Register(FFixedHW, 0x08, 0x18, 0x0000000000000774, 0x04, )},");
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dsdt_line(" Zero,");
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dsdt_line(" Zero,");
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dsdt_line(" Zero");
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dsdt_line(" })");
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dsdt_line(" }");
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}
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void pm_write_dsdt(struct vmctx *ctx, int ncpu)
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{
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int i;
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int ret;
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bool is_cpc = false;
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uint8_t px_cnt;
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/* Scope (_PR) */
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dsdt_line("");
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dsdt_line(" Scope (_SB)");
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dsdt_line(" {");
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for (i = 0; i < ncpu; i++) {
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dsdt_line(" Device (PR%02d)", i);
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dsdt_line(" {");
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dsdt_line(" Name (_HID, \"ACPI0007\")");
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dsdt_line(" Name (_UID, 0x%02X)", i);
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dsdt_line(" }");
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}
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dsdt_line(" }");
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dsdt_line("");
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/* Scope (_PR.CPU(N)) */
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for (i = 0; i < ncpu; i++) {
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dsdt_line(" Scope (_SB.PR%02d)", i);
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dsdt_line(" {");
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dsdt_line("");
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ret = dsdt_write_pss(ctx, i);
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dsdt_write_cst(ctx, i);
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/* if the vm can support px, hv will return the right px/cx cnt.
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then hard code _PPC and _PCT for all vpu */
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if (ret == 0) {
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if (i == 0) {
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dsdt_write_ppc();
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dsdt_write_pct();
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} else {
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dsdt_line(" Method (_PPC, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (^^PR00._PPC)");
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dsdt_line(" }");
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dsdt_line("");
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dsdt_line(" Method (_PCT, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (^^PR00._PCT)");
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dsdt_line(" }");
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dsdt_line("");
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}
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}
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ret = get_vcpu_px_cnt(ctx, i, &px_cnt);
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if (ret == 0 && px_cnt == 0) {
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/* px_cnt = 0 Indicates vcpu supports continuous pstate.
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* Then we can write _CPC
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*/
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is_cpc = true;
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}
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if (is_cpc) {
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if (i == 0) {
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dsdt_write_cpc();
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} else {
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dsdt_line(" Method (_CPC, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (^^PR00._CPC)");
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dsdt_line(" }");
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dsdt_line("");
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}
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}
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dsdt_line(" }");
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}
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}
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/* _OSC: Operating System Capabilities
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* Currently only support CPPC v2 capability.
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* CPPC v2 capability: revision 2 of the _CPC object.
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* If all vcpus don't support _CPC object, no need to add _OSC in DSDT.
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*/
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void osc_write_ospm_dsdt(struct vmctx *ctx, int ncpu)
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{
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int ret;
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bool support_cpc = false;
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uint8_t px_cnt;
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/* check px_cnt on vBSP */
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ret = get_vcpu_px_cnt(ctx, 0, &px_cnt);
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if (ret == 0 && px_cnt == 0) {
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/* px_cnt = 0 Indicates vcpu supports continuous pstate.
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*/
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support_cpc = true;
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}
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if (support_cpc) {
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/* Scope (_SB._OSC) */
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dsdt_line("");
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dsdt_line(" Scope (_SB)");
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dsdt_line(" {");
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dsdt_line(" Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities");
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dsdt_line(" {");
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dsdt_line(" CreateDWordField (Arg3, 0x00, STS0)");
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dsdt_line(" CreateDWordField (Arg3, 0x04, CAP0)");
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dsdt_line(" If ((Arg0 == ToUUID (\"0811b06e-4a27-44f9-8d60-3cbbc22e7b48\") /* Platform-wide OSPM Capabilities */))");
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dsdt_line(" {");
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dsdt_line(" If ((Arg1 == One))");
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dsdt_line(" {");
|
|
dsdt_line(" If ((CAP0 & 0x40))");
|
|
dsdt_line(" {");
|
|
dsdt_line(" CAP0 &= 0x00000040");
|
|
dsdt_line(" }");
|
|
dsdt_line(" Else");
|
|
dsdt_line(" {");
|
|
dsdt_line(" STS0 &= 0xFFFFFF00");
|
|
dsdt_line(" STS0 |= 0x02");
|
|
dsdt_line(" }");
|
|
dsdt_line(" }");
|
|
dsdt_line(" Else");
|
|
dsdt_line(" {");
|
|
dsdt_line(" STS0 &= 0xFFFFFF00");
|
|
dsdt_line(" STS0 |= 0x0A");
|
|
dsdt_line(" }");
|
|
dsdt_line(" }");
|
|
dsdt_line(" Else");
|
|
dsdt_line(" {");
|
|
dsdt_line(" STS0 &= 0xFFFFFF00");
|
|
dsdt_line(" STS0 |= 0x06");
|
|
dsdt_line(" }");
|
|
dsdt_line(" Return (Arg3)");
|
|
dsdt_line(" }");
|
|
dsdt_line(" }");
|
|
dsdt_line("");
|
|
}
|
|
}
|