Conghui Chen 8e4e1c96d1 hv: vuart bugfix for additional byte in tx fifo ...

For communication vuart, when it send data to target vuart's fifo, it
should meet the conditions:

1. MCR_LOOPBACK is not set
2. LCR_DLAB is not set
3. access reg is UART16550_THR
4. target_vu is not null

But the LCR_DLAB is missed now, and when vuart set it's UART16550_DLL,
it will be send to target by mistake as UART16550_DLL = UART16550_THR.
Add the missed condition.

DLAB in uart16550 spec:

Divisor Latch Access Bit.
1 = Allows access to the Divisor Latch Registers and reading of the FIFO
Control Register.
0 = Allows access to RBR, THR, IER and IIR registers.

Tracked-On: #3681
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>

2019-09-17 09:45:28 +08:00

..

vpci

hv: vpci: a minor fix about vpci_init_pt_dev

2019-09-16 15:32:26 +08:00

io_req.c

hv: remove pr_dbg between stac/clac

2019-09-10 09:48:27 +08:00

vioapic.c

softirq:spinlock: correct vioapic/vpic lock usage

2019-07-22 09:55:06 +08:00

vpic.c

hv: remove 'flags' field in struct vm_io_range

2019-08-19 10:19:54 +08:00

vrtc.c

hv: remove 'flags' field in struct vm_io_range

2019-08-19 10:19:54 +08:00

vuart.c

hv: vuart bugfix for additional byte in tx fifo

2019-09-17 09:45:28 +08:00