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fbdc2774af
The design of ACRN CPU performance management is to let hardware
do the autonomous frequency selection(or set to a fixed value),
and remove guest's ability to control CPU frequency.
This patch is to implement the CPU frequency initializer, which will
setup CPU frequency base on the performance policy type.
Two performance policy types are provided for user to choose from:
- 'Performance': CPU runs at its CPU runs at its maximum frequency.
Enable hardware autonomous frequency selection if HWP is presented.
- 'Nominal': CPU runs at its guaranteed frequency.
The policy type is passed to hypervisor through boot parameter, as
either 'cpu_perf_policy=Nominal' or 'cpu_perf_policy=Performance'.
The default type is 'Performance'.
Both HWP and ACPI p-state are supported. HWP is the first choice, for
it provides hardware autonomous frequency selection, while keeps
frequency transaction time low.
Two functions are added to the hypervisor to call:
- init_frequency_policy(): called by BSP at start up time. It processes
the boot parameters, and enables HWP if it is presented.
- apply_frequency_policy(): called after init_frequency_policy().
It applies initial CPU frequency policy setting for each core. It
uses a set of frequency limits data struct to quickly decide what the
highest/nominal frequency is. The frequency limits are generated by
config-tools.
The hypervisor will not be governing CPU frequency after initial policy
is applied.
Cores running RTVMs are fixed to nominal/guaranteed frequency, to get
more certainty in latency. This is done by setting the core's frequency
limits to highest=lowest=nominal in config-tools.
Tracked-On: #8168
Signed-off-by: Wu Zhou <wu.zhou@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HOST_PM_H
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#define HOST_PM_H
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#include <acrn_common.h>
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#define BIT_SLP_TYPx 10U
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#define BIT_SLP_EN 13U
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#define BIT_WAK_STS 15U
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struct cpu_state_info {
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uint8_t px_cnt; /* count of all Px states */
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const struct acrn_pstate_data *px_data;
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uint8_t cx_cnt; /* count of all Cx entries */
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const struct acrn_cstate_data *cx_data;
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};
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struct cpu_state_table {
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char model_name[64];
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struct cpu_state_info state_info;
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};
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struct acpi_reset_reg {
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struct acrn_acpi_generic_address reg;
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uint8_t val;
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};
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struct pm_s_state_data *get_host_sstate_data(void);
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void host_enter_s3(const struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val);
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void shutdown_system(void);
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void save_s5_reg_val(uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val);
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void do_acpi_sx(const struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val);
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extern void asm_enter_s3(const struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val);
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extern void restore_s3_context(void);
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struct cpu_state_info *get_cpu_pm_state_info(void);
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struct acpi_reset_reg *get_host_reset_reg_data(void);
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void reset_host(void);
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void init_frequency_policy(void);
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void apply_frequency_policy(void);
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#endif /* HOST_PM_H */
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