Chenli Wei 8331375172 misc: refine CDP mode ...

The current code use cache type to check whether enable the CDP mode,
then merge policy by clos_mask, sometimes the data and code CLOS is not
continuous.

This patch add a special CDP policy to record and merge policy to fix
this above issue.

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>

2022-05-30 09:23:33 +08:00

..

lib

misc: configurator: Add entry "None" to HV console selector

2022-05-24 17:14:38 +08:00

bdf.py

config-tools: Fix Enable SR-IOV build fail

2022-05-24 16:07:16 +08:00

board_capability.py

misc: add the define of MAX_IR_ENTRIES

2022-05-20 09:08:47 +08:00

clos.py

misc: refine CDP mode

2022-05-30 09:23:33 +08:00

cpu_affinity.py

config_tools: track whether each vCPU is used for real-time or not

2022-04-21 10:08:53 +08:00

gpa.py

config-tools: extract the SSRAM area size

2022-04-18 16:47:23 +08:00

guest_flags.py

misc: set PMU_PT flag for pre-launched RTVM

2022-03-29 09:34:17 +08:00

intx.py

misc: add vUART channel for s5 feature

2022-05-13 13:50:07 +08:00

main.py

misc: fix the issue of create hv node

2022-04-28 13:42:54 +08:00

memory_allocator.py

config_tools: update the hugepage algorithm

2022-05-07 10:51:10 +08:00

pio.py

Remove "All rights reserved" string headers

2022-04-06 13:21:02 +08:00

s5_vuart.py

misc: modify the non stand s5 vUART generate logic

2022-05-24 11:44:03 +08:00