Zide Chen 9323f811ea HV: Prepare cpu_secondary.S for AP trampoline code relocation ... V1->V2: removed CONFIG_LOW_RAM_START and added ".org 0" to cpu_secondary.S The assumption is trampoline code is relocated while HV is not, so: trampoline code is built at address 0, and CS register is updated by SIPI to reflect the correct vector in real mode part, added extra pointers for page tables and long jump buffer so it's possible for HV code to patch the relocation offset in long mode part, use absolute addressing when referring HV symbols, and use relative addressing for symbols within trampoline code Signed-off-by: Zheng, Gen <gen.zheng@intel.com> Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Eddie Dong <eddie.dong> Acked-by: Xu, Anthony <anthony.xu@intel.com>		2018-05-15 17:25:58 +08:00
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include/bsp	HV: Prepare cpu_secondary.S for AP trampoline code relocation	2018-05-15 17:25:58 +08:00
sbl.c	initial import	2018-05-11 14:44:28 +08:00
vm_description.c	remove deadcode of vm1 config in vm_description	2018-05-15 17:25:56 +08:00