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While we hoped to make the headings consistent over time while doing other edits, we should instead just make the squirrels happy and do them all at once or they'll likely never be made consistent. A python script was used to find the headings, and then a call to https://pypi.org/project/titlecase to transform the title. A visual inspection was used to tweak a few unexpected resulting titles. Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
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290 lines
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ReStructuredText
.. _virtual-interrupt-hld:
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Virtual Interrupt
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#################
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This section introduces the ACRN guest virtual interrupt
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management, which includes:
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- VCPU request for virtual interrupt kick off,
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- vPIC/vIOAPIC/vLAPIC for virtual interrupt injection interfaces,
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- physical-to-virtual interrupt mapping for a passthrough device, and
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- the process of VMX interrupt/exception injection.
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A standard VM never owns any physical interrupts; all interrupts received by the
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Guest OS come from a virtual interrupt injected by vLAPIC, vIOAPIC, or
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vPIC. Such virtual interrupts are triggered either from a passthrough
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device or from I/O mediators in the Service VM via hypercalls. The
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:ref:`interrupt-remapping` section discusses how the hypervisor manages
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the mapping between physical and virtual interrupts for passthrough
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devices. However, a hard RT VM with LAPIC passthrough does own the physical
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maskable external interrupts. On its physical CPUs, interrupts are disabled
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in VMX root mode, while in VMX non-root mode, physical interrupts will be
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delivered to RT VM directly.
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Emulation for devices is inside the Service VM user space device model, i.e.,
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acrn-dm. However, for performance consideration, vLAPIC, vIOAPIC, and vPIC
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are emulated inside HV directly.
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From the guest OS point of view, vPIC is Virtual Wire Mode via vIOAPIC. The
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symmetric I/O Mode is shown in :numref:`pending-virt-interrupt` later in
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this section.
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The following command line
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options to guest Linux affects whether it uses PIC or IOAPIC:
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- **Kernel boot param with vPIC**: add "maxcpu=0" Guest OS will use PIC
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- **Kernel boot param with vIOAPIC**: add "maxcpu=1" (as long as not "0")
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Guest OS will use IOAPIC. And Keep IOAPIC pin2 as source of PIC.
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.. _vcpu-request-interrupt-injection:
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vCPU Request for Interrupt Injection
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************************************
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The vCPU request mechanism (described in :ref:`pending-request-handlers`) is leveraged
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to inject interrupts to a certain vCPU. As mentioned in
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:ref:`ipi-management`,
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physical vector 0xF0 is used to kick VCPU out of its VMX non-root mode,
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used to make a request for virtual interrupt injection or other
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requests such as flush EPT.
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.. note:: the IPI based vCPU request mechanism doesn't work for the hard RT VM.
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The eventid supported for virtual interrupt injection includes:
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.. doxygengroup:: virt_int_injection
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:project: Project ACRN
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:content-only:
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The *vcpu_make_request* is necessary for a virtual interrupt
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injection. If the target vCPU is running under VMX non-root mode, it
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will send an IPI to kick it out, which leads to an external-interrupt
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VM-Exit. In some cases, there is no need to send IPI when making a request,
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because the CPU making the request itself is the target VCPU. For
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example, the #GP exception request always happens on the current CPU when it
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finds an invalid emulation has happened. An external interrupt for a passthrough
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device always happens on the VCPUs of the VM which this device is belonged to,
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so after it triggers an external-interrupt VM-Exit, the current CPU is the very
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target VCPU.
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Virtual LAPIC
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*************
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LAPIC is virtualized for all Guest types: Service and User VMs. Given support
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by the physical processor, APICv Virtual Interrupt Delivery (VID) is enabled
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and will support Posted-Interrupt feature. Otherwise, it will fall back to
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the legacy virtual interrupt injection mode.
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vLAPIC provides the same features as the native LAPIC:
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- Vector mask/unmask
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- Virtual vector injections (Level or Edge trigger mode) to vCPU
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- vIOAPIC notification of EOI processing
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- TSC Timer service
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- vLAPIC support CR8 to update TPR
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- INIT/STARTUP handling
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vLAPIC APIs
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===========
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APIs are invoked when an interrupt source from vLAPIC needs to inject
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an interrupt, for example:
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- from LVT like LAPIC timer
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- from vIOAPIC for a passthrough device interrupt
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- from an emulated device for a MSI
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These APIs will finish by making a vCPU request.
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.. doxygenfunction:: vlapic_inject_intr
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:project: Project ACRN
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.. doxygenfunction:: vlapic_set_intr
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:project: Project ACRN
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.. doxygenfunction:: vlapic_set_local_intr
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:project: Project ACRN
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.. doxygenfunction:: vlapic_inject_msi
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:project: Project ACRN
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.. doxygenfunction:: vlapic_receive_intr
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:project: Project ACRN
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EOI Processing
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==============
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EOI virtualization is enabled if APICv virtual interrupt delivery is
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supported. Except for level triggered interrupts, the VM will not exit in
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case of EOI.
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In case of no APICv virtual interrupt delivery support, vLAPIC requires
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EOI from Guest OS whenever a vector was acknowledged and processed by
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guest. vLAPIC behavior is the same as HW LAPIC. Once an EOI is received,
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it clears the highest priority vector in ISR, and updates PPR
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status. vLAPIC will send an EOI message to vIOAPIC if the TMR bit is set to
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indicate that is a level triggered interrupt.
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.. _lapic_passthru:
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LAPIC Passthrough Based on vLAPIC
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=================================
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LAPIC passthrough is supported based on vLAPIC, the guest OS first boots with
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vLAPIC in xAPIC mode and then switches to x2APIC mode to enable the LAPIC
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passthrough.
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In case of LAPIC passthrough based on vLAPIC, the system will have the
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following characteristics.
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* IRQs received by the LAPIC can be handled by the Guest VM without ``vmexit``
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* Guest VM always see virtual LAPIC IDs for security consideration
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* most MSRs are directly accessible from Guest VM except for ``XAPICID``,
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``LDR`` and ``ICR``. Write operations to ``ICR`` will be trapped to avoid
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malicious IPIs. Read operations to ``XAPIC`` and ``LDR`` will be trapped in
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order to make the Guest VM always see the virtual LAPIC IDs instead of the
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physical ones.
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Virtual IOAPIC
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**************
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vIOAPIC is emulated by HV when Guest accesses MMIO GPA range:
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0xFEC00000-0xFEC01000. vIOAPIC for Service VM should match to the native HW
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IOAPIC Pin numbers. vIOAPIC for guest VM provides 48 pins. As the vIOAPIC is
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always associated with vLAPIC, the virtual interrupt injection from
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vIOAPIC will finally trigger a request for vLAPIC event by calling
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vLAPIC APIs.
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**Supported APIs:**
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.. doxygenfunction:: vioapic_set_irqline_lock
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:project: Project ACRN
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.. doxygenfunction:: vioapic_set_irqline_nolock
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:project: Project ACRN
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Virtual PIC
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***********
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vPIC is required for TSC calculation. Normally guest OS will boot with
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vIOAPIC and vPIC as the source of external interrupts. On every
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VM Exit, HV will check if there are any pending external PIC interrupts.
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vPIC APIs usage are similar to vIOAPIC.
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ACRN hypervisor emulates a vPIC for each VM based on IO range 0x20~0x21,
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0xa0~0xa1 and 0x4d0~0x4d1.
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If an interrupt source from vPIC need to inject an interrupt, the
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following APIs need be called, which will finally make a request for
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*ACRN_REQUEST_EXTINT or ACRN_REQUEST_EVENT*:
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.. doxygenfunction:: vpic_set_irqline
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:project: Project ACRN
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The following APIs are used to query the vector needed to be injected and ACK
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the service (means move the interrupt from request service - IRR to in
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service - ISR):
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.. doxygenfunction:: vpic_pending_intr
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:project: Project ACRN
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.. doxygenfunction:: vpic_intr_accepted
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:project: Project ACRN
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Virtual Exception
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*****************
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When doing emulation, an exception may need to be triggered in
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hypervisor, for example:
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- if guest accesses an invalid vMSR register,
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- hypervisor needs to inject a #GP, or
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- hypervisor needs to inject #PF when an instruction accesses a non-exist page
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from rip_gva during instruction emulation.
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ACRN hypervisor implements virtual exception injection using these APIs:
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.. doxygenfunction:: vcpu_queue_exception
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:project: Project ACRN
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.. doxygenfunction:: vcpu_inject_gp
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:project: Project ACRN
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.. doxygenfunction:: vcpu_inject_pf
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:project: Project ACRN
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.. doxygenfunction:: vcpu_inject_ud
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:project: Project ACRN
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.. doxygenfunction:: vcpu_inject_ss
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:project: Project ACRN
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ACRN hypervisor uses the *vcpu_inject_gp/vcpu_inject_pf* functions
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to queue exception request, and follows SDM vol3 - 6.15, Table 6-5 to
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generate double fault if the condition is met.
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ACRN hypervisor could inject *extint/nmi* using the similar vcpu APIs:
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.. doxygenfunction:: vcpu_inject_extint
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:project: Project ACRN
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.. doxygenfunction:: vcpu_inject_nmi
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:project: Project ACRN
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.. _virt-interrupt-injection:
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Virtual Interrupt Injection
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***************************
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The source of virtual interrupts comes from either DM or assigned
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devices.
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- **For Service VM assigned devices**: as most devices are assigned to the
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Service VM directly. Whenever there is a physical interrupt from an assigned
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device, the corresponding virtual interrupt will be injected to the Service
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VM via vLAPIC/vIOAPIC. See :ref:`device-assignment`.
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- **For User VM assigned devices**: only PCI devices could be assigned to
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User VM. For the standard VM and soft RT VM, the virtual interrupt
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injection follows the same way as Service VM. A virtual interrupt injection
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operation is triggered when a device's physical interrupt occurs. For the
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hard RT VM, the physical interrupts are delivered to VM directly without
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causing VM-exit.
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- **For User VM emulated devices**: DM is responsible for the
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emulated devices' interrupt lifecycle management. DM knows when
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an emulated device needs to assert a virtual IOPAIC/PIC Pin or
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needs to send a virtual MSI vector to Guest. These logic is
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entirely handled by DM. For the hard RT VM, there should be no
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emulated devices.
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.. figure:: images/virtint-image64.png
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:align: center
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:name: pending-virt-interrupt
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Handle pending virtual interrupt
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Before APICv virtual interrupt delivery, a virtual interrupt can be
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injected only if guest interrupt is allowed. There are many cases
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that Guest ``RFLAGS.IF`` gets cleared and it would not accept any further
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interrupts. HV will check for the available Guest IRQ windows before
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injection.
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NMI is unmaskable interrupt and its injection is always allowed
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regardless of the guest IRQ window status. If current IRQ
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window is not present, HV would enable
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``MSR_IA32_VMX_PROCBASED_CTLS_IRQ_WIN (PROCBASED_CTRL.bit[2])`` and
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VM Enter directly. The injection will be done on next VM Exit once Guest
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issues ``STI (GuestRFLAG.IF=1)``.
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Data Structures and Interfaces
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******************************
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There is no data structure exported to the other components in the
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hypervisor for virtual interrupts. The APIs listed in the previous
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sections are meant to be called whenever a virtual interrupt should be
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injected or acknowledged.
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