Files
acrn-hypervisor/hypervisor/arch/x86
Yan, Like 97916364fc hv: fix virtual TSC_DEADLINE msr read/write issues
When write to virtual TSC_DEADLINE, if virtual TSC_ADJUST is not zero:
 - when guest intends to disarm the tsc_deadline timer, should not arm the timer falsely;
 - when guest intends to arm the tsc_deadline timer, should not disarm the timer falsely.

When read from virtual TSC_DEADLINE, if virtual TSC_ADJUST is not zero:
 - if physical TSC_DEADLINE is not zero, return the virtual TSC_DEADLINE value;
 - if physical TSC_DEADLINE is zero which means it's not armed (automatically disarmed after
   timer triggered), return 0 and reset the virtual TSC_DEADLINE.

Tracked-On: #4162
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-12-02 16:10:50 +08:00
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