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https://github.com/projectacrn/acrn-hypervisor.git
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65e4a16e6a
There're some platforms still doesn't support 1GB large page on CPU side. Such as lakefield, TNT and EHL platforms on which have some silicon bug and this case CPU don't support 1GB large page. This patch tries to release this constrain to support more hardware platform. Note this patch doesn't release the constrain on IOMMU side. Tracked-On: #4550 Signed-off-by: Li Fei1 <fei1.li@intel.com>
295 lines
10 KiB
C
295 lines
10 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <rtl.h>
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#include <cpufeatures.h>
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#include <pgtable.h>
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#include <page.h>
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#include <mmu.h>
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#include <trusty.h>
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#include <vtd.h>
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#include <security.h>
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#include <vm.h>
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#define LINEAR_ADDRESS_SPACE_48_BIT (1UL << 48U)
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static struct page ppt_pml4_pages[PML4_PAGE_NUM(LINEAR_ADDRESS_SPACE_48_BIT)];
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static struct page ppt_pdpt_pages[PDPT_PAGE_NUM(LINEAR_ADDRESS_SPACE_48_BIT)];
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static struct page ppt_pd_pages[PD_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE + PLATFORM_LO_MMIO_SIZE)];
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/* ppt: pripary page table */
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static union pgtable_pages_info ppt_pages_info = {
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.ppt = {
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.pml4_base = ppt_pml4_pages,
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.pdpt_base = ppt_pdpt_pages,
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.pd_base = ppt_pd_pages,
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}
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};
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/* @pre: The PPT and EPT have same page granularity */
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static inline bool large_page_support(enum _page_table_level level)
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{
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bool support;
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if (level == IA32E_PD) {
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support = true;
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} else if (level == IA32E_PDPT) {
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support = pcpu_has_vmx_ept_cap(VMX_EPT_1GB_PAGE);
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} else {
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support = false;
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}
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return support;
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}
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static inline uint64_t ppt_get_default_access_right(void)
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{
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return (PAGE_PRESENT | PAGE_RW | PAGE_USER);
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}
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static inline void ppt_clflush_pagewalk(const void* entry __attribute__((unused)))
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{
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}
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static inline uint64_t ppt_pgentry_present(uint64_t pte)
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{
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return pte & PAGE_PRESENT;
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}
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static inline struct page *ppt_get_pml4_page(const union pgtable_pages_info *info)
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{
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struct page *pml4_page = info->ppt.pml4_base;
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(void)memset(pml4_page, 0U, PAGE_SIZE);
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return pml4_page;
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}
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static inline struct page *ppt_get_pdpt_page(const union pgtable_pages_info *info, uint64_t gpa)
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{
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struct page *pdpt_page = info->ppt.pdpt_base + (gpa >> PML4E_SHIFT);
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(void)memset(pdpt_page, 0U, PAGE_SIZE);
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return pdpt_page;
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}
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static inline struct page *ppt_get_pd_page(const union pgtable_pages_info *info, uint64_t gpa)
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{
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struct page *pd_page = info->ppt.pd_base + (gpa >> PDPTE_SHIFT);
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(void)memset(pd_page, 0U, PAGE_SIZE);
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return pd_page;
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}
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static inline void nop_tweak_exe_right(uint64_t *entry __attribute__((unused))) {}
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static inline void nop_recover_exe_right(uint64_t *entry __attribute__((unused))) {}
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const struct memory_ops ppt_mem_ops = {
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.info = &ppt_pages_info,
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.large_page_support = large_page_support,
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.get_default_access_right = ppt_get_default_access_right,
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.pgentry_present = ppt_pgentry_present,
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.get_pml4_page = ppt_get_pml4_page,
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.get_pdpt_page = ppt_get_pdpt_page,
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.get_pd_page = ppt_get_pd_page,
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.clflush_pagewalk = ppt_clflush_pagewalk,
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.tweak_exe_right = nop_tweak_exe_right,
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.recover_exe_right = nop_recover_exe_right,
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};
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static struct page sos_vm_pml4_pages[SOS_VM_NUM][PML4_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page sos_vm_pdpt_pages[SOS_VM_NUM][PDPT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page sos_vm_pd_pages[SOS_VM_NUM][PD_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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/* pre_uos_nworld_pml4_pages */
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static struct page pre_uos_nworld_pml4_pages[PRE_VM_NUM][PML4_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page pre_uos_nworld_pdpt_pages[PRE_VM_NUM][PDPT_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page pre_uos_nworld_pd_pages[PRE_VM_NUM][PD_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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/* post_uos_nworld_pml4_pages */
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static struct page post_uos_nworld_pml4_pages[MAX_POST_VM_NUM][PML4_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page post_uos_nworld_pdpt_pages[MAX_POST_VM_NUM][PDPT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page post_uos_nworld_pd_pages[MAX_POST_VM_NUM][PD_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page post_uos_sworld_pgtable_pages[MAX_POST_VM_NUM][TRUSTY_PGTABLE_PAGE_NUM(TRUSTY_RAM_SIZE)];
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/* pre-assumption: TRUSTY_RAM_SIZE is 2M aligned */
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static struct page post_uos_sworld_memory[MAX_POST_VM_NUM][TRUSTY_RAM_SIZE >> PAGE_SHIFT] __aligned(MEM_2M);
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/* ept: extended page table*/
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static union pgtable_pages_info ept_pages_info[CONFIG_MAX_VM_NUM];
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#ifdef CONFIG_LAST_LEVEL_EPT_AT_BOOT
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/* Array with address space size for each type of load order of VM */
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static const uint64_t vm_address_space_size[MAX_LOAD_ORDER] = {
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PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE), /* for Pre-Launched VM */
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EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE), /* for SOS VM */
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EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE), /* for Post-Launched VM */
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};
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/*
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* @brief Reserve space for EPT 4K pages from platform E820 table
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*/
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void reserve_buffer_for_ept_pages(void)
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{
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uint64_t pt_base;
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uint16_t vm_id;
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uint32_t offset = 0U;
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struct acrn_vm_config *vm_config;
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pt_base = e820_alloc_memory(TOTAL_EPT_4K_PAGES_SIZE, ~0UL);
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hv_access_memory_region_update(pt_base, TOTAL_EPT_4K_PAGES_SIZE);
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for (vm_id = 0U; vm_id < CONFIG_MAX_VM_NUM; vm_id++) {
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vm_config = get_vm_config(vm_id);
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ept_pages_info[vm_id].ept.nworld_pt_base = (struct page *)(void *)(pt_base + offset);
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offset += PT_PAGE_NUM(vm_address_space_size[vm_config->load_order])*MEM_4K;
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}
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}
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#else
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static struct page sos_vm_pt_pages[SOS_VM_NUM][PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page pre_uos_nworld_pt_pages[PRE_VM_NUM][PT_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page post_uos_nworld_pt_pages[MAX_POST_VM_NUM][PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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#endif
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void *get_reserve_sworld_memory_base(void)
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{
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return post_uos_sworld_memory;
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}
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static inline bool large_page_not_support(__unused enum _page_table_level level)
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{
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return false;
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}
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static inline uint64_t ept_get_default_access_right(void)
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{
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return EPT_RWX;
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}
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static inline uint64_t ept_pgentry_present(uint64_t pte)
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{
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return pte & EPT_RWX;
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}
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static inline void ept_clflush_pagewalk(const void* etry)
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{
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iommu_flush_cache(etry, sizeof(uint64_t));
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}
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static inline struct page *ept_get_pml4_page(const union pgtable_pages_info *info)
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{
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struct page *pml4_page = info->ept.nworld_pml4_base;
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(void)memset(pml4_page, 0U, PAGE_SIZE);
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return pml4_page;
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}
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static inline struct page *ept_get_pdpt_page(const union pgtable_pages_info *info, uint64_t gpa)
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{
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struct page *pdpt_page = info->ept.nworld_pdpt_base + (gpa >> PML4E_SHIFT);
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(void)memset(pdpt_page, 0U, PAGE_SIZE);
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return pdpt_page;
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}
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static inline struct page *ept_get_pd_page(const union pgtable_pages_info *info, uint64_t gpa)
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{
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struct page *pd_page;
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if (gpa < TRUSTY_EPT_REBASE_GPA) {
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pd_page = info->ept.nworld_pd_base + (gpa >> PDPTE_SHIFT);
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} else {
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pd_page = info->ept.sworld_pgtable_base + TRUSTY_PML4_PAGE_NUM(TRUSTY_EPT_REBASE_GPA) +
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TRUSTY_PDPT_PAGE_NUM(TRUSTY_EPT_REBASE_GPA) + ((gpa - TRUSTY_EPT_REBASE_GPA) >> PDPTE_SHIFT);
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}
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(void)memset(pd_page, 0U, PAGE_SIZE);
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return pd_page;
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}
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static inline struct page *ept_get_pt_page(const union pgtable_pages_info *info, uint64_t gpa)
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{
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struct page *pt_page;
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if (gpa < TRUSTY_EPT_REBASE_GPA) {
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pt_page = info->ept.nworld_pt_base + (gpa >> PDE_SHIFT);
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} else {
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pt_page = info->ept.sworld_pgtable_base + TRUSTY_PML4_PAGE_NUM(TRUSTY_EPT_REBASE_GPA) +
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TRUSTY_PDPT_PAGE_NUM(TRUSTY_EPT_REBASE_GPA) + TRUSTY_PD_PAGE_NUM(TRUSTY_EPT_REBASE_GPA) +
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((gpa - TRUSTY_EPT_REBASE_GPA) >> PDE_SHIFT);
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}
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(void)memset(pt_page, 0U, PAGE_SIZE);
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return pt_page;
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}
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static inline void *ept_get_sworld_memory_base(const union pgtable_pages_info *info)
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{
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return info->ept.sworld_memory_base;
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}
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/* The function is used to disable execute right for (2MB / 1GB)large pages in EPT */
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static inline void ept_tweak_exe_right(uint64_t *entry)
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{
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*entry &= ~EPT_EXE;
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}
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/* The function is used to recover the execute right when large pages are breaking into 4KB pages
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* Hypervisor doesn't control execute right for guest memory, recovers execute right by default.
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*/
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static inline void ept_recover_exe_right(uint64_t *entry)
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{
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*entry |= EPT_EXE;
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}
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void init_ept_mem_ops(struct memory_ops *mem_ops, uint16_t vm_id)
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{
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struct acrn_vm *vm = get_vm_from_vmid(vm_id);
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if (is_sos_vm(vm)) {
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ept_pages_info[vm_id].ept.top_address_space = EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE);
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ept_pages_info[vm_id].ept.nworld_pml4_base = sos_vm_pml4_pages[0U];
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ept_pages_info[vm_id].ept.nworld_pdpt_base = sos_vm_pdpt_pages[0U];
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ept_pages_info[vm_id].ept.nworld_pd_base = sos_vm_pd_pages[0U];
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#ifndef CONFIG_LAST_LEVEL_EPT_AT_BOOT
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ept_pages_info[vm_id].ept.nworld_pt_base = sos_vm_pt_pages[0U];
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#endif
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} else if (is_prelaunched_vm(vm)) {
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ept_pages_info[vm_id].ept.top_address_space = PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE);
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ept_pages_info[vm_id].ept.nworld_pml4_base = pre_uos_nworld_pml4_pages[vm_id];
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ept_pages_info[vm_id].ept.nworld_pdpt_base = pre_uos_nworld_pdpt_pages[vm_id];
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ept_pages_info[vm_id].ept.nworld_pd_base = pre_uos_nworld_pd_pages[vm_id];
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#ifndef CONFIG_LAST_LEVEL_EPT_AT_BOOT
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ept_pages_info[vm_id].ept.nworld_pt_base = pre_uos_nworld_pt_pages[vm_id];
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#endif
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} else {
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uint16_t sos_vm_id = (get_sos_vm())->vm_id;
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uint16_t page_idx = vmid_2_rel_vmid(sos_vm_id, vm_id) - 1U;
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ept_pages_info[vm_id].ept.top_address_space = EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE);
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ept_pages_info[vm_id].ept.nworld_pml4_base = post_uos_nworld_pml4_pages[page_idx];
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ept_pages_info[vm_id].ept.nworld_pdpt_base = post_uos_nworld_pdpt_pages[page_idx];
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ept_pages_info[vm_id].ept.nworld_pd_base = post_uos_nworld_pd_pages[page_idx];
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#ifndef CONFIG_LAST_LEVEL_EPT_AT_BOOT
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ept_pages_info[vm_id].ept.nworld_pt_base = post_uos_nworld_pt_pages[page_idx];
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#endif
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ept_pages_info[vm_id].ept.sworld_pgtable_base = post_uos_sworld_pgtable_pages[page_idx];
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ept_pages_info[vm_id].ept.sworld_memory_base = post_uos_sworld_memory[page_idx];
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mem_ops->get_sworld_memory_base = ept_get_sworld_memory_base;
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}
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mem_ops->info = &ept_pages_info[vm_id];
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mem_ops->get_default_access_right = ept_get_default_access_right;
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mem_ops->pgentry_present = ept_pgentry_present;
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mem_ops->get_pml4_page = ept_get_pml4_page;
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mem_ops->get_pdpt_page = ept_get_pdpt_page;
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mem_ops->get_pd_page = ept_get_pd_page;
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mem_ops->get_pt_page = ept_get_pt_page;
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mem_ops->clflush_pagewalk = ept_clflush_pagewalk;
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mem_ops->large_page_support = large_page_support;
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/* Mitigation for issue "Machine Check Error on Page Size Change" */
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if (is_ept_force_4k_ipage()) {
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mem_ops->tweak_exe_right = ept_tweak_exe_right;
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mem_ops->recover_exe_right = ept_recover_exe_right;
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/* For RTVM, build 4KB page mapping in EPT */
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if (is_rt_vm(vm)) {
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mem_ops->large_page_support = large_page_not_support;
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}
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} else {
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mem_ops->tweak_exe_right = nop_tweak_exe_right;
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mem_ops->recover_exe_right = nop_recover_exe_right;
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}
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}
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