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https://github.com/projectacrn/acrn-hypervisor.git
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a68f655a11
For a pre-launched VM, a region from PTDEV_HI_MMIO_START is used to store 64bit vBARs of PT devices which address is high than 4G. The region should be located after all user memory space and be coverd by guest EPT address. Tracked-On: #4458 Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
66 lines
3.8 KiB
C
66 lines
3.8 KiB
C
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* BIOS Information
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* Vendor: American Megatrends Inc.
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* Version: WL10R104
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* Release Date: 09/12/2019
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* BIOS Revision: 5.13
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*
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* Base Board Information
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* Manufacturer: Maxtang
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* Product Name: WL10
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* Version: V1.0
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*/
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#ifndef PCI_DEVICES_H_
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#define PCI_DEVICES_H_
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#define PTDEV_HI_MMIO_SIZE 0UL
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#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}
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#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}, \
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.vbar_base[0] = 0xa0000000UL, \
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.vbar_base[2] = 0x90000000UL
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#define SIGNAL_PROCESSING_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x00U}, \
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.vbar_base[0] = 0xa141e000UL
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#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}, \
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.vbar_base[0] = 0xa1400000UL
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#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U}, \
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.vbar_base[0] = 0xa1416000UL, \
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.vbar_base[2] = 0xa141d000UL
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#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}, \
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.vbar_base[0] = 0xa141c000UL
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#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}, \
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.vbar_base[0] = 0xa1414000UL, \
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.vbar_base[1] = 0xa141b000UL, \
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.vbar_base[5] = 0xa141a000UL
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#define SD_HOST_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x00U}, \
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.vbar_base[0] = 0xa1419000UL
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#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U}
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#define PCI_BRIDGE_1 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x04U}
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#define PCI_BRIDGE_2 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x00U}
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#define PCI_BRIDGE_3 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x01U}
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#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U}
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#define AUDIO_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U}, \
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.vbar_base[0] = 0xa1410000UL, \
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.vbar_base[4] = 0xa1000000UL
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#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U}, \
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.vbar_base[0] = 0xa1418000UL
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#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U}, \
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.vbar_base[0] = 0xfe010000UL
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#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x00U}, \
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.vbar_base[0] = 0xa1300000UL
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#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x00U}, \
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.vbar_base[0] = 0xa1200000UL, \
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.vbar_base[3] = 0xa1220000UL
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#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x04U, .d = 0x00U, .f = 0x00U}, \
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.vbar_base[0] = 0xa1100000UL, \
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.vbar_base[3] = 0xa1120000UL
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#endif /* PCI_DEVICES_H_ */
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