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https://github.com/projectacrn/acrn-hypervisor.git
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dadcdcefa0
To support cpu sharing, multiple vcpu can run on same pcpu. We need do necessary vcpu context switch. This patch add below actions in context switch. 1) fxsave/fxrstor; 2) save/restore MSRs: MSR_IA32_STAR, MSR_IA32_LSTAR, MSR_IA32_FMASK, MSR_IA32_KERNEL_GS_BASE; 3) switch vmcs. Tracked-On: #3813 Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Signed-off-by: Yu Wang <yu1.wang@intel.com> Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VMCS_H_
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#define VMCS_H_
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#define VM_SUCCESS 0
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#define VM_FAIL -1
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#ifndef ASSEMBLER
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#include <types.h>
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#include <vcpu.h>
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#define VMX_VMENTRY_FAIL 0x80000000U
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#define APIC_ACCESS_OFFSET 0xFFFUL /* 11:0, offset within the APIC page */
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#define APIC_ACCESS_TYPE 0xF000UL /* 15:12, access type */
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#define TYPE_LINEAR_APIC_INST_READ (0UL << 12U)
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#define TYPE_LINEAR_APIC_INST_WRITE (1UL << 12U)
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/* VM exit qulifications for APIC-access
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* Access type:
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* 0 = linear access for a data read during instruction execution
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* 1 = linear access for a data write during instruction execution
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* 2 = linear access for an instruction fetch
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* 3 = linear access (read or write) during event delivery
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* 10 = guest-physical access during event delivery
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* 15 = guest-physical access for an instructon fetch or during
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* instruction execution
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*/
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static inline uint64_t apic_access_type(uint64_t qual)
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{
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return (qual & APIC_ACCESS_TYPE);
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}
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static inline uint64_t apic_access_offset(uint64_t qual)
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{
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return (qual & APIC_ACCESS_OFFSET);
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}
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void init_vmcs(struct acrn_vcpu *vcpu);
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void switch_vmcs(const struct acrn_vcpu *vcpu);
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void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu);
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#endif /* ASSEMBLER */
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#endif /* VMCS_H_ */
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