Jian Jun Chen 9d6ec75628 [FIXME] hv: riscv: add a stub do_logmsg for build ...

This is just for temporary build and should be reverted when
common debug module is integrated.

Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>

2025-09-23 11:30:38 +08:00

..

boot

hv: risc-v: add assembly code for BSP and AP boot

2025-09-15 13:12:21 +08:00

guest

…

cpu.c

hv: multiarch: riscv: add two cpu interfaces

2025-09-19 15:04:55 +08:00

dummy_entry.S

…

dummy.c

…

init.c

hv: risc-v: add C entry function of BSP and APs

2025-09-15 13:12:21 +08:00

link_ram.ld.in

hv: risc-v: update link script

2025-09-15 13:12:21 +08:00

logmsg.c

[FIXME] hv: riscv: add a stub do_logmsg for build

2025-09-23 11:30:38 +08:00

Makefile

[FIXME] hv: riscv: add a stub do_logmsg for build

2025-09-23 11:30:38 +08:00

notify.c

hv: ipi: drop arch_ prefix from IPI functions

2025-09-19 13:56:21 +08:00

sbi.c

hv: riscv: add SBI HSM HART_START interface

2025-09-23 11:30:38 +08:00

timer.c

risc-v: initial timer codes

2025-09-17 08:55:12 +08:00

trap.c

risc-v: handle timer interrupt

2025-09-17 08:55:12 +08:00

trap.h

risc-v: handle timer interrupt

2025-09-17 08:55:12 +08:00