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acrn-hypervisor/hypervisor/include/arch
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Yonghua Huang 9e8c1a1508 hv: reset CAT Capacity Bitmask(CBM) MSRs 
ACRN get messy default values for some CAT CBM MSRs,
  these unexpected default value will result in TCC
  Software SRAM initializes crash.

  This patch resets above error default values before calling
  CRL(cache reserve library) ABI initializaion function.

Tracked-On: #6780
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2021-11-12 16:25:35 +08:00
..
x86/asm
hv: reset CAT Capacity Bitmask(CBM) MSRs
2021-11-12 16:25:35 +08:00