acrn-hypervisor/hypervisor/arch/x86/guest
dongshen a07c3da3da hv: define posted interrupt IRQs/vectors
This is a preparation patch for adding support for VT-d PI
related vCPU scheduling.

ACRN does not support vCPU migration, one vCPU always runs on
the same pCPU, so PI's ndst is never changed after startup.

VCPUs of a VM won’t share same pCPU. So the maximum possible number
of VCPUs that can run on a pCPU is CONFIG_MAX_VM_NUM.

Allocate unique Activation Notification Vectors (ANV) for each vCPU
that belongs to the same pCPU, the ANVs need only be unique within each
pCPU, not across all vCPUs. This reduces # of pre-allocated ANVs for
posted interrupts to CONFIG_MAX_VM_NUM, and enables ACRN to avoid
switching between active and wake-up vector values in the posted
interrupt descriptor on vCPU scheduling state changes.

A total of CONFIG_MAX_VM_NUM consecutive IRQs/vectors are reserved
for posted interrupts use.

The code first initializes vcpu->arch.pid.control.bits.nv dynamically
(will be added in subsequent patch), the other code shall use
vcpu->arch.pid.control.bits.nv instead of the hard-coded notification vectors.

Rename some functions:
  apicv_post_intr --> apicv_trigger_pi_anv
  posted_intr_notification --> handle_pi_notification
  setup_posted_intr_notification --> setup_pi_notification

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-04-16 13:47:23 +08:00
..
assign.c hv: check if the IRQ is intended for a single destination vCPU 2020-04-16 13:47:23 +08:00
ept.c hv: add lock for ept add/modify/del 2020-04-15 08:36:46 +08:00
guest_memory.c hv: rename the ACRN_DBG_XXX 2020-01-14 10:21:23 +08:00
hyperv.c hv: rename the ACRN_DBG_XXX 2020-01-14 10:21:23 +08:00
instr_emul.c hv: instr_emul: use cs segment when fetching instructions 2019-11-11 13:55:24 +08:00
pm.c hv:Rename two VM states 2020-03-13 10:34:29 +08:00
trusty.c hv: support xsave in context switch 2019-12-02 09:31:12 +08:00
ucode.c hv:cleanup header file for guest folder 2019-02-21 10:38:30 +08:00
vcpu.c hv: define posted interrupt IRQs/vectors 2020-04-16 13:47:23 +08:00
vcpuid.c hv: cpuid: expose PCID related capabilities to VMs 2020-01-02 10:47:34 +08:00
ve820.c HV: move create_sos_vm_e820 to ve820.c 2020-03-12 14:56:34 +08:00
virq.c hv: fix for waag 2 core reboot issue 2020-04-15 10:20:01 +08:00
virtual_cr.c hv: cr: handle control registers related to PCID 2020-01-02 10:47:34 +08:00
vlapic_priv.h hv: add ops to vlapic structure 2019-07-19 16:47:06 +08:00
vlapic.c hv: define posted interrupt IRQs/vectors 2020-04-16 13:47:23 +08:00
vm_reset.c hv:Rename two VM states 2020-03-13 10:34:29 +08:00
vm.c hv: add function to check if using posted interrupt is possible for vm 2020-04-16 13:47:23 +08:00
vmcall.c hv: vPCI: remove passthrough PCI device unuse code 2020-02-24 16:17:38 +08:00
vmcs.c hv: define posted interrupt IRQs/vectors 2020-04-16 13:47:23 +08:00
vmexit.c hv: HLT emulation in hypervisor 2020-01-07 11:23:32 +08:00
vmsr.c HV: CAT: support cache allocation for each vcpu 2020-04-10 16:11:42 +08:00
vmtrr.c hv: refine 'uint64_t' string print format in x86 moudle 2019-11-09 11:42:38 +08:00
vmx_asm.S hv:remove some unnecessary includes 2019-05-07 09:10:13 +08:00
vmx_io.c hv: rename BOOT_CPU_ID to BSP_CPU_ID 2020-02-25 09:08:14 +08:00