Binbin Wu a0a6eb43c4 hv: msr: use UL since ia32_misc_enable is 64bit ... Merge two parts of different definitions for MSR_IA32_MISC_ENABLE fields. - use the prefix "MSR_IA32_" to align with others - Change MSR_IA32_MISC_ENABLE_XD to MSR_IA32_MISC_ENABLE_XD_DISABLE to align the meaning of the filed since it is "XD bit disable" Use UL instead of U as the filed bit mask because MSR_IA32_MISC_ENABLE is 64-bit. Tracked-On: #2834 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2019-05-09 16:35:15 +08:00
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x86	hv: msr: use UL since ia32_misc_enable is 64bit	2019-05-09 16:35:15 +08:00