Binbin Wu a0a6eb43c4 hv: msr: use UL since ia32_misc_enable is 64bit ... Merge two parts of different definitions for MSR_IA32_MISC_ENABLE fields. - use the prefix "MSR_IA32_" to align with others - Change MSR_IA32_MISC_ENABLE_XD to MSR_IA32_MISC_ENABLE_XD_DISABLE to align the meaning of the filed since it is "XD bit disable" Use UL instead of U as the filed bit mask because MSR_IA32_MISC_ENABLE is 64-bit. Tracked-On: #2834 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2019-05-09 16:35:15 +08:00
..
arch/x86	hv: msr: use UL since ia32_misc_enable is 64bit	2019-05-09 16:35:15 +08:00
common	hv: release IOMMU irte when releasing ptirq remapping entries	2019-05-06 18:25:37 +08:00
debug	HV: vuart: support MSR and MCR	2019-04-29 15:25:39 +08:00
dm	HV: rename 'type' in struct io_request	2019-05-06 18:25:20 +08:00
hw	hv: move pci.h to include/hw	2019-04-12 10:09:26 +08:00
lib	hv:remove some unnecessary includes	2019-05-07 09:10:13 +08:00
public	hv: add new hypercall to fetch platform configurations	2019-04-15 22:14:13 +08:00