Binbin Wu 5c81659713 hv: ept: flush cache for modified ept entries ...

EPT tables are shared by MMU and IOMMU.
Some IOMMUs don't support page-walk coherency, the cpu cache of EPT entires
should be flushed to memory after modifications, so that the modifications
are visible to the IOMMUs.

This patch adds a new interface to flush the cache of modified EPT entires.
There are different implementations for EPT/PPT entries:
- For PPT, there is no need to flush the cpu cache after update.
- For EPT, need to call iommu_flush_cache to make the modifications visible
to IOMMUs.

Tracked-On: #3607
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>

2019-08-26 10:47:17 +08:00

..

arch/x86

hv: ept: flush cache for modified ept entries

2019-08-26 10:47:17 +08:00

common

hv: schedule: minor fix about the return type of need_offline

2019-07-17 09:20:54 +08:00

debug

hv: uart: enable early boot uart

2019-07-26 09:10:06 +08:00

dm

hv: remove 'flags' field in struct vm_io_range

2019-08-19 10:19:54 +08:00

hw

hv: vpci: refine init_vdevs

2019-08-06 11:51:02 +08:00

lib

hv:move several files related X86 for lib

2019-05-13 10:12:20 +08:00

public

HV: add kata support on sdc scenario

2019-07-12 16:34:31 +08:00