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https://github.com/projectacrn/acrn-hypervisor.git
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65927b4f03
add stack_frame definition, and implement acrh_switch_to for riscv. Tracked-On: #8812 Signed-off-by: Xue Bosheng <bosheng.xue@intel.com> Signed-off-by: Haicheng Li <haicheng.li@outlook.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
84 lines
1.7 KiB
ArmAsm
84 lines
1.7 KiB
ArmAsm
/*
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* Copyright (C) 2023-2025 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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.text
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.align 8
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.global arch_switch_to
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arch_switch_to:
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/* refer to struct stack_frame */
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addi sp, sp, -0x80
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/*
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* 0x0=STACK_FRAME_OFFSET_RA
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* 0x8=STACK_FRAME_OFFSET_S0
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* 0x10=STACK_FRAME_OFFSET_S1
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* 0x18=STACK_FRAME_OFFSET_S2
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* 0x20=STACK_FRAME_OFFSET_S3
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* 0x28=STACK_FRAME_OFFSET_S4
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* 0x30=STACK_FRAME_OFFSET_S5
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* 0x38=STACK_FRAME_OFFSET_S6
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* 0x40=STACK_FRAME_OFFSET_S7
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* 0x48=STACK_FRAME_OFFSET_S8
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* 0x50=STACK_FRAME_OFFSET_S9
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* 0x58=STACK_FRAME_OFFSET_S10
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* 0x60=STACK_FRAME_OFFSET_S11
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* 0x68=STACK_FRAME_OFFSET_A0
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*/
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sd ra, 0x0(sp)
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sd s0, 0x8(sp)
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sd s1, 0x10(sp)
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sd s2, 0x18(sp)
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sd s3, 0x20(sp)
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sd s4, 0x28(sp)
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sd s5, 0x30(sp)
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sd s6, 0x38(sp)
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sd s7, 0x40(sp)
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sd s8, 0x48(sp)
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sd s9, 0x50(sp)
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sd s10, 0x58(sp)
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sd s11, 0x60(sp)
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sd a0, 0x68(sp)
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sd sp, 0(a0)
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ld sp, 0(a1)
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/*
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* 0x0=STACK_FRAME_OFFSET_RA
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* 0x8=STACK_FRAME_OFFSET_S0
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* 0x10=STACK_FRAME_OFFSET_S1
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* 0x18=STACK_FRAME_OFFSET_S2
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* 0x20=STACK_FRAME_OFFSET_S3
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* 0x28=STACK_FRAME_OFFSET_S4
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* 0x30=STACK_FRAME_OFFSET_S5
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* 0x38=STACK_FRAME_OFFSET_S6
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* 0x40=STACK_FRAME_OFFSET_S7
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* 0x48=STACK_FRAME_OFFSET_S8
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* 0x50=STACK_FRAME_OFFSET_S9
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* 0x58=STACK_FRAME_OFFSET_S10
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* 0x60=STACK_FRAME_OFFSET_S11
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* 0x68=STACK_FRAME_OFFSET_A0
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*/
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ld ra, 0x0(sp)
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ld s0, 0x8(sp)
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ld s1, 0x10(sp)
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ld s2, 0x18(sp)
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ld s3, 0x20(sp)
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ld s4, 0x28(sp)
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ld s5, 0x30(sp)
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ld s6, 0x38(sp)
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ld s7, 0x40(sp)
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ld s8, 0x48(sp)
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ld s9, 0x50(sp)
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ld s10, 0x58(sp)
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ld s11, 0x60(sp)
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ld a0, 0x68(sp)
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addi sp, sp, 0x80
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ret
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