hangliu1 a436f72493 hv: riscv: add access usr memory interface ...

Add pre_user_access() and post_user_access() interfaces
to protect mmio from hypervisor accidental access,
SMAP extensiton need to be detected

Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>

2025-10-21 14:14:55 +08:00

..

cpu.c

log: move print_hv_banner as common

2025-10-14 14:45:12 +08:00

delay.c

…

efi_mmap.c

…

event.c

…

hv_main.c

hv: move run_idle_thread to schedule file

2025-09-30 12:31:07 +08:00

hypercall.c

hv: riscv: add access usr memory interface

2025-10-21 14:14:55 +08:00

irq.c

…

logmsg.c

…

mmu.c

hv: multiarch: add arch specific set_pgentry

2025-10-21 14:14:55 +08:00

notify.c

…

percpu.c

…

ptdev.c

…

sbuf.c

hv: riscv: add access usr memory interface

2025-10-21 14:14:55 +08:00

sched_bvt.c

…

sched_iorr.c

hv: fix build issue in schedule module

2025-09-30 12:31:07 +08:00

sched_noop.c

hv: fix build issue in schedule module

2025-09-30 12:31:07 +08:00

sched_prio.c

hv: fix build issue in schedule module

2025-09-30 12:31:07 +08:00

schedule.c

hv: move run_idle_thread to schedule file

2025-09-30 12:31:07 +08:00

softirq.c

…

thermal.c

…

ticks.c

…

timer.c

…

trace.c

…

trusty_hypercall.c

…

vm_event.c

hv: riscv: add access usr memory interface

2025-10-21 14:14:55 +08:00

vm_load.c

…