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https://github.com/projectacrn/acrn-hypervisor.git
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52e7919d9f
Add hypervisor pagetable manipulate interface to riscv arch directory, which is needed by the common interface, and add riscv ppt pgtable structure implementation. Tracked-On: #8831 Signed-off-by: Haicheng Li <haicheng.li@intel.com> Co-developed-by: hangliu1 <hang1.liu@intel.com> Signed-off-by: hangliu1 <hang1.liu@intel.com> Reviewed-by: Fei Li <fei1.li@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
/*
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* Copyright (C) 2018-2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RISCV_PGTABLE_H
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#define RISCV_PGTABLE_H
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#include <asm/page.h>
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/* FIXME: Temporary RISC-V build workaround
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* This file provides hva2hpa[_early] and hpa2hva[_early] function stubs to
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* satisfy existing code dependencies. Remove this file and migrate to the
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* common pgtable.h implementation once the MMU module is properly integrated.
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*/
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static inline void *hpa2hva_early(uint64_t x)
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{
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return (void *)x;
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}
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static inline uint64_t hva2hpa_early(void *x)
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{
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return (uint64_t)x;
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}
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#define SATP_MODE_SV48 0x9000000000000000UL
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#define SATP_PPN_MASK 0x00000FFFFFFFFFFFUL
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#define PG_TABLE_SHIFT 9UL
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#define PG_TABLE_ENTRIES (_AC(1,U) << PG_TABLE_SHIFT)
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#define PG_TABLE_ENTRY_MASK (PG_TABLE_ENTRIES - 1)
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#define BIT0 0x00000001UL
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#define BIT1 0x00000002UL
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#define BIT2 0x00000004UL
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#define BIT3 0x00000008UL
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#define BIT4 0x00000010UL
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#define BIT5 0x00000020UL
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#define BIT6 0x00000040UL
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#define BIT7 0x00000080UL
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#define BIT8 0x00000100UL
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#define BIT9 0x00000200UL
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#define BIT10 0x00000400UL
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#define BIT11 0x00000800UL
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#define BIT12 0x00001000UL
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#define BIT13 0x00002000UL
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#define BIT14 0x00004000UL
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#define BIT15 0x00008000UL
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#define PTE_ENTRY_COUNT 512UL
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#define PTE_ADDR_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 10UL)
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#define PAGE_ATTR_MASK (((uint64_t)0x3UL) << 61UL)
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#define PAGE_ATTR_PMA (0x0UL)
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#define PAGE_ATTR_UC (((uint64_t)0x1UL) << 61UL)
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#define PAGE_ATTR_IO (((uint64_t)0x2UL) << 61UL)
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#define PAGE_ATTR_RSV (((uint64_t)0x3UL) << 61UL)
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#define PAGE_CONF_MASK 0xffUL
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#define PAGE_V BIT0
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#define PAGE_R BIT1
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#define PAGE_W BIT2
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#define PAGE_X BIT3
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#define PAGE_U BIT4
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#define PAGE_G BIT5
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#define PAGE_A BIT6
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#define PAGE_D BIT7
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#define PAGE_TYPE_MASK 0xfUL
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#define PAGE_TYPE_TABLE (0x0UL | PAGE_V)
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#define PAGE_NO_RW (PAGE_V | PAGE_R | PAGE_W)
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#define PAGE_RW_RW (PAGE_V | PAGE_U | PAGE_R | PAGE_W)
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#define PAGE_NO_RO (PAGE_V | PAGE_R)
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#define PAGE_RO_RO (PAGE_V | PAGE_U | PAGE_R)
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#define PAGE_ATTRIBUTES_MASK (PAGE_CONF_MASK | PAGE_ATTR_MASK)
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#define DEFINE_PAGE_TABLES(name, nr) \
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pgtable_t __aligned(PAGE_SIZE) name[PG_TABLE_ENTRIES * (nr)]
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#define DEFINE_PAGE_TABLE(name) DEFINE_PAGE_TABLES(name, 1)
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#define PTE_PFN_MASK 0x3FFFFFFFFFFC00UL
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#define PAGE_BASE_OFFSET 10UL
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/* for Sv48, vpn0 shift is 12 */
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#define PTE_SHIFT (PAGE_SHIFT)
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#define PTRS_PER_PTE (PG_TABLE_ENTRIES)
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/* for Sv48, vpn1 shift is 21 */
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#define VPN1_SHIFT (PTE_SHIFT + PG_TABLE_SHIFT)
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#define PTRS_PER_VPN1 (PG_TABLE_ENTRIES)
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/* for Sv48, vpn2 shift is 30 */
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#define VPN2_SHIFT (VPN1_SHIFT + PG_TABLE_SHIFT)
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#define PTRS_PER_VPN2 (PG_TABLE_ENTRIES)
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/* for Sv48, vpn3 shift is 39 */
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#define VPN3_SHIFT (VPN2_SHIFT + PG_TABLE_SHIFT)
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#define PTRS_PER_VPN3 (PG_TABLE_ENTRIES)
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#define PAGE_PFN_MASK 0x0000FFFFFFFFF000UL
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#define PFN_MASK PTE_PFN_MASK
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#define PPT_PFN_HIGH_MASK 0xFFFF000000000000UL
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#define INVALID_HPA (0x1UL << 52U)
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#ifndef __ASSEMBLY__
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#define IS_ALIGNED(val, align) (((val) & ((align) - 1)) == 0)
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#ifdef __ASSEMBLY__
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#define _AC(X,Y) X
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#define _AT(T,X) X
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#else
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#define __AC(X,Y) (X##Y)
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#define _AC(X,Y) __AC(X,Y)
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#define _AT(T,X) ((T)(X))
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#endif
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struct page {
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uint8_t contents[PAGE_SIZE];
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} __aligned(PAGE_SIZE);
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typedef uint64_t pgtable_t;
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/*
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* Memory Type
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*/
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#define MT_PMA 0x0UL
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#define MT_UC 0x1UL
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#define MT_IO 0x2UL
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#define MT_RSV 0x3UL
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#endif /* __ASSEMBLY__ */
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#endif /* RISCV_PGTABLE_H */
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