mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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fc495b946a
This patch implements interrupt initialization and the basic exception/interrupt handling flow on RISC-V. init_interrupt() needs to be invoked during CPU initialization to set up the trap vector and enable the interrupt. RISC-V exception and interrupt handling includes: - Saving and restoring CPU registers around traps - Implementing handlers for: - Supervisor software interrupt - Supervisor timer interrupt - Halting the CPU for all other interrupts and exceptions ------ TODOs: 1. add support for registering interrupt handlers via request_irq() and further adoption of the common IRQ framework. 2. add support for external interrupt. Tracked-On: #8813 Signed-off-by: Haicheng Li <haicheng.li@intel.com> Co-developed-by: Shiqing Gao <shiqing.gao@intel.com> Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
64 lines
2.2 KiB
C
64 lines
2.2 KiB
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#ifndef RISCV_TRAP_H
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#define RISCV_TRAP_H
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#define TRAP_VECTOR_MODE_DIRECT 0U
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#define TRAP_VECTOR_MODE_VECTORED 1U
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/**
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* The Interrupt bit (most significant bit) in the scause register
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* is set if the trap was caused by an interrupt.
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*/
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#define TRAP_CAUSE_INTERRUPT_BITMASK (1UL << 63U)
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/* Trap Cause Codes - Interrupt */
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/* Software Interrupt */
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#define TRAP_CAUSE_IRQ_S_SOFT 1UL /* Supervisor software interrupt */
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#define TRAP_CAUSE_IRQ_VS_SOFT 2UL /* Virtual supervisor software interrupt */
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#define TRAP_CAUSE_IRQ_M_SOFT 3UL /* Machine software interrupt */
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/* Timer Interrupt */
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#define TRAP_CAUSE_IRQ_S_TIMER 5UL /* Supervisor timer interrupt */
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#define TRAP_CAUSE_IRQ_VS_TIMER 6UL /* Virtual supervisor timer interrupt */
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#define TRAP_CAUSE_IRQ_M_TIMER 7UL /* Machine timer interrupt */
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/* External Interrupt */
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#define TRAP_CAUSE_IRQ_S_EXT 9UL /* Supervisor external interrupt */
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#define TRAP_CAUSE_IRQ_VS_EXT 10UL /* Virtual supervisor external interrupt */
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#define TRAP_CAUSE_IRQ_M_EXT 11UL /* Machine external interrupt */
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#define TRAP_CAUSE_IRQ_S_GUEST_EXT 12UL /* Supervisor guest external interrupt */
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#define TRAP_CAUSE_IRQ_COUNTER_OVF 13UL /* Reserved for counter-overflow interrupt */
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/* Interrupt Pending/Enable registers flags */
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/* Software Interrupt */
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#define IP_IE_SSI (1UL << TRAP_CAUSE_IRQ_S_SOFT)
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#define IP_IE_VSSI (1UL << TRAP_CAUSE_IRQ_VS_SOFT)
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#define IP_IE_MSI (1UL << TRAP_CAUSE_IRQ_M_SOFT)
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/* Timer Interrupt */
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#define IP_IE_STI (1UL << TRAP_CAUSE_IRQ_S_TIMER)
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#define IP_IE_VSTI (1UL << TRAP_CAUSE_IRQ_VS_TIMER)
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#define IP_IE_MTI (1UL << TRAP_CAUSE_IRQ_M_TIMER)
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/* External Interrupt */
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#define IP_IE_SEI (1UL << TRAP_CAUSE_IRQ_S_EXT)
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#define IP_IE_VSEI (1UL << TRAP_CAUSE_IRQ_VS_EXT)
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#define IP_IE_MEI (1UL << TRAP_CAUSE_IRQ_M_EXT)
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#define IP_IE_SGEI (1UL << TRAP_CAUSE_IRQ_S_GUEST_EXT)
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#define IP_IE_LCOFI (1UL << TRAP_CAUSE_IRQ_COUNTER_OVF)
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#ifndef ASSEMBLER
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#include <asm/irq.h>
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extern uint64_t strap_handler;
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void dispatch_trap(const struct intr_excp_ctx *ctx);
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#endif /* ASSEMBLER */
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#endif /* RISCV_TRAP_H */
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