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5d8f5023d0
hv: vpci: inject physical PCIEXBAR to SOS vhostbridge in order to fully emulate a full host bridge following HW spec The vhostbridge we emulate currently is a "Celeron N3350/ Pentium N4200/Atom E3900 Series Host Bridge", which is of Appollo Lake SoC, but the emulation is incomplete, and we need to implement a full vhostbridge following HW spec. This is a step-by-step process, and in this patch we fixes the simulation of PCIEXBAR register (0x60) and thus solved bug #6464. -------#6464: SOS cannot make use of ECAM--------------- Generally, SOS will check the MMIO Base Addr in ACPI MCFG table to confirm it is a reserved memory area. There will be 3 methods to check: 1. Via E820 table 2. Via EFI runtime service 3. To check with the value in PCIEXBAR(0x60) of hostbridge For SOS, method 2 is not feasible since no EFI runtime service is available for SOS. And on newer platform like EHL/TGL, its BIOS somehow doesn't reserve it in native E820, thus SOS will try use method 3 to verify, so we should inject physical ECAM to vhostbridge, otherwise all 3 methods will fail, and SOS will not make use of ECAM, which will results in that SOS cannot use PCIe Extended Capabilities like SR-IOV. ------------------------------------------------------- TODO: 1. In the future, we may add one or more virtual hostbridges for CPUs that are incompatible in layout with the current one, according to HW specs 2. Besides PCIEXBAR(0x60), there are also some registers needs to be emulated more precisely rather than be treated as read-only and hard-coded, will be fixed in future patches. Tracked-On: #5056 Signed-off-by: Qian Wang <qian1.wang@intel.com> Reviewed-by: Jason Chen <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>