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https://github.com/projectacrn/acrn-hypervisor.git
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a6420e8cfa
This patch updates below terminologies according to the latest TCC Spec: PTCT -> RTCT PTCM -> RTCM pSRAM -> Software SRAM Tracked-On: #5649 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RTCT_H
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#define RTCT_H
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#include <acpi.h>
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#define RTCT_ENTRY_TYPE_RTCD_LIMIT 1U
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#define RTCT_ENTRY_TYPE_RTCM_BINARY 2U
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#define RTCT_ENTRY_TYPE_WRC_L3_MASKS 3U
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#define RTCT_ENTRY_TYPE_GT_L3_MASKS 4U
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#define RTCT_ENTRY_TYPE_SOFTWARE_SRAM 5U
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#define RTCT_ENTRY_TYPE_STREAM_DATAPATH 6U
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#define RTCT_ENTRY_TYPE_TIMEAWARE_SUBSYS 7U
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#define RTCT_ENTRY_TYPE_RT_IOMMU 8U
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#define RTCT_ENTRY_TYPE_MEM_HIERARCHY_LATENCY 9U
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#define SOFTWARE_SRAM_BASE_HPA 0x40080000U
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#define SOFTWARE_SRAM_BASE_GPA 0x40080000U
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#define SOFTWARE_SRAM_MAX_SIZE 0x00800000U
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struct rtct_entry {
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uint16_t size;
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uint16_t format;
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uint32_t type;
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uint32_t data[64];
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} __packed;
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struct rtct_entry_data_rtcm_binary
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{
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uint64_t address;
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uint32_t size;
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} __packed;
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struct rtct_entry_data_software_sram
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{
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uint32_t cache_level;
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uint64_t base;
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uint32_t ways;
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uint32_t size;
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uint32_t apic_id_0; /*only the first core is responsible for initialization of L3 mem region*/
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} __packed;
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extern uint64_t software_sram_area_bottom;
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extern uint64_t software_sram_area_top;
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#endif /* RTCT_H */
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