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a6614e7e2f
In v3.0 the msrfield class has its initializer changed in a way that is incompatible with the parameter names or the getter/setter. When introduced from the BITS project, that class allows specifying an MSR field of arbitrary length by being given the index of the most and least significant bits. This patch restores the original behavior of that msrfield class and moves the use-case specific methods, namely is_vmx_cap_supported and is_ctrl_setting_allowed, to a helper class. Parsing of the VMX capability reporting MSRs in msr.py are updated accordingly, and brief documentation of the MSR fields are added as well. Tracked-On: #7948 Signed-off-by: Junjie Mao <junjie.mao@intel.com>
258 lines
7.7 KiB
Python
258 lines
7.7 KiB
Python
# Copyright (C) 2022 Intel Corporation.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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from cpuparser.platformbase import MSR, msrfield
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class MSR_IA32_MISC_ENABLE(MSR):
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addr = 0x1a0
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fast_string = msrfield(0, 0, doc="Fast-strings enable")
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capability_bits = [
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"fast_string",
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]
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class MSR_IA32_FEATURE_CONTROL(MSR):
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addr = 0x03a
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lock = msrfield(0, 0, doc="Lock bit")
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vmx_outside_smx = msrfield(2, 2, doc="Enable VMX outside SMX operation")
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@property
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def disable_vmx(self):
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return self.lock and not self.vmx_outside_smx
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capability_bits = [
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"disable_vmx",
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]
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class VMXCapabilityReportingMSR(MSR):
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def get_field_idx(self, field):
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if isinstance(field, int):
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return field
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if isinstance(field, str):
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return getattr(type(self), field).lsb
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assert False, f"Invalid field type: {field}, {type(field)}"
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def allows_0_setting(self, field):
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field_idx = self.get_field_idx(field)
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if field_idx >= 32:
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return False
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bit_mask = (1 << field_idx)
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return (self.value & bit_mask) == 0
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def allows_1_setting(self, field):
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field_idx = self.get_field_idx(field)
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if field_idx >= 32:
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return False
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bit_mask = (1 << field_idx)
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high = self.value >> 32
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return (high & bit_mask) == bit_mask
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def allows_flexible_setting(self, field):
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field_idx = self.get_field_idx(field)
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return self.allows_0_setting(field_idx) and self.allows_1_setting(field_idx)
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class MSR_IA32_VMX_PROCBASED_CTLS2(VMXCapabilityReportingMSR):
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addr = 0x0000048B
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vapic_access = msrfield(0, 0, doc="Virtualize APIC accesses")
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ept = msrfield(1, 1, doc="Enable EPT")
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rdtscp = msrfield(3, 3, doc="Enable RDTSCP")
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vx2apic = msrfield(4, 4, doc="Virtualize x2APIC mode")
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vpid = msrfield(5, 5, doc="Enable VPID")
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unrestricted_guest = msrfield(7, 7, doc="Unrestricted guest")
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apic_reg_virt = msrfield(8, 8, doc="APIC-register virtualization")
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@property
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def vmx_procbased_ctls2_vapic(self):
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return self.allows_flexible_setting("vapic_access")
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@property
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def vmx_procbased_ctls2_ept(self):
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return self.allows_flexible_setting("ept")
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@property
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def vmx_procbased_ctls2_vpid(self):
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return self.allows_flexible_setting("vpid")
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@property
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def vmx_procbased_ctls2_rdtscp(self):
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return self.allows_flexible_setting("rdtscp")
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@property
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def vmx_procbased_ctls2_unrestrict(self):
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return self.allows_flexible_setting("unrestricted_guest")
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capability_bits = [
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"vmx_procbased_ctls2_vapic",
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"vmx_procbased_ctls2_ept",
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"vmx_procbased_ctls2_vpid",
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"vmx_procbased_ctls2_rdtscp",
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"vmx_procbased_ctls2_unrestrict",
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]
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class MSR_IA32_VMX_PINBASED_CTLS(VMXCapabilityReportingMSR):
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addr = 0x00000481
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irq_exiting = msrfield(0, 0, doc="External-interrupt existing")
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@property
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def vmx_pinbased_ctls_irq_exit(self):
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return self.allows_flexible_setting("irq_exiting")
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capability_bits = [
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"vmx_pinbased_ctls_irq_exit",
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]
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class MSR_IA32_VMX_PROCBASED_CTLS(VMXCapabilityReportingMSR):
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addr = 0x00000482
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tsc_offsetting = msrfield(3, 3, doc="Use TSC offsetting")
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hlt_exiting = msrfield(7, 7, doc="HLT exiting")
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tpr_shadow = msrfield(21, 21, doc="Use TPR shadow")
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io_bitmaps = msrfield(25, 25, doc="Use I/O bitmaps")
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msr_bitmaps = msrfield(28, 28, doc="Use MSR bitmaps")
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secondary_ctrls = msrfield(31, 31, doc="Activate secondary controls")
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@property
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def vmx_procbased_ctls_tsc_off(self):
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return self.allows_flexible_setting("tsc_offsetting")
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@property
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def vmx_procbased_ctls_tpr_shadow(self):
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return self.allows_flexible_setting("tpr_shadow")
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@property
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def vmx_procbased_ctls_io_bitmap(self):
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return self.allows_flexible_setting("io_bitmaps")
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@property
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def vmx_procbased_ctls_msr_bitmap(self):
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return self.allows_flexible_setting("msr_bitmaps")
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@property
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def vmx_procbased_ctls_hlt(self):
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return self.allows_flexible_setting("hlt_exiting")
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@property
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def vmx_procbased_ctls_secondary(self):
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return self.allows_flexible_setting("secondary_ctrls")
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@property
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def ept(self):
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if self.allows_1_setting("secondary_ctrls"):
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ctls2 = MSR_IA32_VMX_PROCBASED_CTLS2.rdmsr(self.cpu_id)
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return ctls2.allows_1_setting("ept")
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return False
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@property
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def apicv(self):
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if not self.allows_1_setting("tpr_shadow"):
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return False
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ctls2 = MSR_IA32_VMX_PROCBASED_CTLS2.rdmsr(self.cpu_id)
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return \
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ctls2.allows_1_setting("vapic_access") and \
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ctls2.allows_1_setting("vx2apic")
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capability_bits = [
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"ept",
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"apicv",
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"vmx_procbased_ctls_tsc_off",
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"vmx_procbased_ctls_tpr_shadow",
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"vmx_procbased_ctls_io_bitmap",
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"vmx_procbased_ctls_msr_bitmap",
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"vmx_procbased_ctls_hlt",
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"vmx_procbased_ctls_secondary",
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]
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class MSR_IA32_VMX_EPT_VPID_CAP(MSR):
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addr = 0x0000048C
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invept = msrfield(20, 20, doc="INVEPT instruction supported")
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ept_2mb_page = msrfield(16, 16, doc="EPT 2-Mbyte page supported")
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vmx_ept_1gb_page = msrfield(17, 17, doc="EPT 1-Gbyte page supported")
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invvpid_inst = msrfield(32, 32, doc="INVVPID instruction supported")
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invvpid_single_context = msrfield(41, 41, doc="single-context INVVPID type supported")
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invvpid_all_context = msrfield(42, 42, doc="all-context INVVPID type supported")
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@property
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def invvpid(self):
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return self.invvpid_inst and self.invvpid_single_context and self.invvpid_all_context
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capability_bits = [
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"invept",
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"invvpid",
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"ept_2mb_page",
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"vmx_ept_1gb_page",
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]
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class MSR_IA32_VMX_MISC(MSR):
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addr = 0x00000485
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stores_lma_on_exit = msrfield(5, 5, doc="VM exits stores the value of IA32_EFER.LMA into the 'IA-32e mode guest' VM-entry control")
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capability_bits = [
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"stores_lma_on_exit",
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]
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class MSR_IA32_VMX_BASIC(MSR):
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addr = 0x00000480
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set_32bit_addr_width = msrfield(48, 48, doc="Addresses of VMXON, VMCS and referenced structures limited to 32-bit")
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capability_bits = [
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"set_32bit_addr_width",
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]
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class MSR_IA32_VMX_EXIT_CTLS(VMXCapabilityReportingMSR):
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addr = 0x00000483
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host_addr_size = msrfield(9, 9, doc="Host address-space size")
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ack_irq_on_exit = msrfield(15, 15, doc="Acknowledge interrupt on exit")
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save_pat = msrfield(18, 18, doc="Save IA32_PAT")
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load_pat = msrfield(19, 19, doc="Load IA32_PAT")
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@property
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def vmx_exit_ctls_ack_irq(self):
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return self.allows_flexible_setting("ack_irq_on_exit")
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@property
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def vmx_exit_ctls_save_pat(self):
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return self.allows_flexible_setting("save_pat")
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@property
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def vmx_exit_ctls_load_pat(self):
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return self.allows_flexible_setting("load_pat")
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@property
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def vmx_exit_ctls_host_addr64(self):
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return self.allows_flexible_setting("host_addr_size")
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capability_bits = [
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"vmx_exit_ctls_ack_irq",
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"vmx_exit_ctls_save_pat",
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"vmx_exit_ctls_load_pat",
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"vmx_exit_ctls_host_addr64",
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]
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class MSR_IA32_VMX_ENTRY_CTLS(VMXCapabilityReportingMSR):
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addr = 0x00000484
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ia32e_mode_guest = msrfield(9, 9, doc="IA-32e mode guest")
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load_pat = msrfield(14, 14, doc="Load IA32_PAT")
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@property
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def vmx_entry_ctls_load_pat(self):
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return self.allows_flexible_setting("load_pat")
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@property
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def vmx_entry_ctls_ia32e_mode(self):
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return self.allows_flexible_setting("ia32e_mode_guest")
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capability_bits = [
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"vmx_entry_ctls_load_pat",
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"vmx_entry_ctls_ia32e_mode",
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]
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