Victor Sun 8f0b0472f6 HV: correct RO mask of MSI cap structure ...

In MSI Capability Structure, bit 7 (64 bit address capable) of MSICTRL
is RO;

Tracked-On: #5125

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Li Fei <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

2020-08-03 13:40:27 +08:00

..

pci_pt.c

HV: ptdev hide SRIOV capability for VM

2020-07-16 17:27:18 +08:00

vdev.c

HV: refine pci_find_vdev with hash

2020-06-18 12:58:40 +08:00

vhostbridge.c

HV: inject physical PCIEXBAR to SOS vhostbridge

2020-07-23 20:20:13 +08:00

vmsi.c

HV: correct RO mask of MSI cap structure

2020-08-03 13:40:27 +08:00

vmsix_on_msi.c

hv: vmsi: add vmsix on msi emulation support

2020-06-16 08:52:56 +08:00

vmsix.c

hv: vpci: minor refine about MSI/MSI-X de-initialization

2020-07-02 13:03:36 +08:00

vpci_bridge.c

hv: vpci: minor refine the vdev ownership data structure

2020-05-13 14:31:01 +08:00

vpci_priv.h

HV: vdev passthough hidding SRIOV

2020-07-16 17:27:18 +08:00

vpci.c

HV: fix hide all sriov in ecap

2020-07-27 11:10:36 +08:00

vsriov.c

HV: vdev passthough hidding SRIOV

2020-07-16 17:27:18 +08:00