Yonghua Huang a6e666dbe7 hv: remove hardcoding of SW SRAM HPA base ... Physical address to SW SRAM region maybe different on different platforms, this hardcoded address may result in address mismatch for SW SRAM operations. This patch removes above hardcoded address and uses the physical address parsed from native RTCT. Tracked-On: #5649 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com> Reviewed-by: Fei Li <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2021-01-28 11:29:25 +08:00
..
event.c	hv: reset vcpu events in reset_vcpu	2020-02-23 16:27:57 +08:00
hv_main.c	hv:add per-vm lock for vm & vcpu state change	2020-07-20 11:22:17 +08:00
hypercall.c	hv: remove hardcoding of SW SRAM HPA base	2021-01-28 11:29:25 +08:00
ptdev.c	hv:unify spin_lock initialization	2020-07-02 09:40:29 +08:00
sched_bvt.c	hv: list: rename list_entry to container_of	2020-03-31 10:57:47 +08:00
sched_iorr.c	hv: sched_iorr: add some interfaces implementation of sched_iorr	2019-12-11 09:31:39 +08:00
sched_noop.c	hv: sched: decouple scheduler from schedule framework	2019-10-25 13:00:21 +08:00
schedule.c	hv: Fix thread status mess if wake_thread() happens in transition stage	2020-08-20 10:32:31 +08:00
softirq.c	softirq: move softirq from hv_main to interrupt context	2019-07-22 09:55:06 +08:00
trusty_hypercall.c	hv: rename the ACRN_DBG_XXX	2020-01-14 10:21:23 +08:00
vm_load.c	hv: modularization: change of multiboot API.	2021-01-27 15:59:47 +08:00