mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-12 18:34:24 +00:00
9c1caad25a
Guest may not use INVEPT instruction after enabling any of bits 2:0 from 0 to 1 of a present EPT entry, then the shadow EPT entry has no chance to sync guest EPT entry. According to the SDM, """ Software may use the INVEPT instruction after modifying a present EPT paging-structure entry (see Section 28.2.2) to change any of the privilege bits 2:0 from 0 to 1.1 Failure to do so may cause an EPT violation that would not otherwise occur. Because an EPT violation invalidates any mappings that would be used by the access that caused the EPT violation (see Section 28.3.3.1), an EPT violation will not recur if the original access is performed again, even if the INVEPT instruction is not executed. """ Sync the afterthought of privilege bits from guest EPT entry to shadow EPT entry to cover above case. Tracked-On: #5923 Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com> |
||
|---|---|---|
| .. | ||
| assign.c | ||
| ept.c | ||
| guest_memory.c | ||
| hyperv.c | ||
| instr_emul.c | ||
| nested.c | ||
| pm.c | ||
| splitlock.c | ||
| trusty.c | ||
| ucode.c | ||
| vcpu.c | ||
| vcpuid.c | ||
| ve820.c | ||
| vept.c | ||
| virq.c | ||
| virtual_cr.c | ||
| vlapic_priv.h | ||
| vlapic.c | ||
| vm_reset.c | ||
| vm.c | ||
| vmcall.c | ||
| vmcs.c | ||
| vmexit.c | ||
| vmsr.c | ||
| vmtrr.c | ||
| vmx_asm.S | ||
| vmx_io.c | ||