Files
acrn-hypervisor/hypervisor/arch/riscv/init.c
Jian Jun Chen b854a24109 hv: risc-v: add C entry function of BSP and APs
Tracked-On: #8788
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-09-15 13:12:21 +08:00

30 lines
473 B
C

/*
* Copyright (C) 2025 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Authors:
* Haicheng Li <haicheng.li@intel.com>
*/
#include <types.h>
/* C entry point for boot CPU */
void init_primary_pcpu(uint64_t hart_id, uint64_t fdt_paddr)
{
(void)hart_id;
(void)fdt_paddr;
while (1) {
asm volatile("wfi" : : : "memory");
}
}
/* C entry point for AP */
void init_secondary_pcpu(uint64_t hart_id)
{
(void)hart_id;
/* to be implemented */
}