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https://github.com/projectacrn/acrn-hypervisor.git
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aa3febbe26
For arch specific codes, we use arch_xxx() to name the function. So, rename cpu_ticks/cpu_tickrate/set_hw_timeout/init_hw_timer to follow this convention. Then, use arch interface to set timeout value in update_physical_timer(). Furthermore, remove hw_timer.h and move its contents into common/ timer.h. Tracked-On: #8792 Signed-off-by: Yi Y Sun <yi.y.sun@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/*
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <softirq.h>
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#include <irq.h>
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#include <logmsg.h>
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#include <timer.h>
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#include <asm/cpu.h>
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#include <asm/msr.h>
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#include <asm/irq.h>
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#include <asm/apicreg.h>
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/* run in interrupt context */
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static void timer_expired_handler(__unused uint32_t irq, __unused void *data)
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{
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fire_softirq(SOFTIRQ_TIMER);
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}
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void arch_set_timer_count(uint64_t cnt)
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{
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msr_write(MSR_IA32_TSC_DEADLINE, cnt);
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}
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void arch_init_timer(void)
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{
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int32_t retval = 0;
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if (get_pcpu_id() == BSP_CPU_ID) {
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retval = request_irq(TIMER_IRQ, timer_expired_handler, NULL, IRQF_NONE);
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if (retval < 0) {
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pr_err("Timer setup failed");
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}
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}
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if (retval >= 0) {
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uint32_t val = TIMER_VECTOR;
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val |= APIC_LVTT_TM_TSCDLT; /* TSC deadline and unmask */
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msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, val);
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/* SDM 10.5.4.1: In x2APIC mode, the processor ensures the
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ordering of this write and any subsequent WRMSR to the
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deadline; no fencing is required. */
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/* disarm timer */
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msr_write(MSR_IA32_TSC_DEADLINE, 0UL);
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}
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}
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