mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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58ab26ea38
- fix code style: mix of tab and white spaces, alignments, etc. - remove not meaningful comments. Also these comments are below the source code which makes the code look messy. - add more MSR register definitions Tracked-On: #1867 Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
511 lines
19 KiB
C
511 lines
19 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MSR_H
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#define MSR_H
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/* architectural (common) MSRs */
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/* Machine check address for MC exception handler */
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#define MSR_IA32_P5_MC_ADDR 0x00000000U
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/* Machine check error type for MC exception handler */
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#define MSR_IA32_P5_MC_TYPE 0x00000001U
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/* System coherence line size for MWAIT/MONITOR */
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#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006U
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#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010U
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#define MSR_IA32_PLATFORM_ID 0x00000017U
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#define MSR_IA32_APIC_BASE 0x0000001BU
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#define MSR_IA32_FEATURE_CONTROL 0x0000003AU
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#define MSR_IA32_TSC_ADJUST 0x0000003BU
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/* Speculation Control */
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#define MSR_IA32_SPEC_CTRL 0x00000048U
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/* Prediction Command */
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#define MSR_IA32_PRED_CMD 0x00000049U
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#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079U
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#define MSR_IA32_BIOS_SIGN_ID 0x0000008BU
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#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008CU
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#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008DU
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#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008EU
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#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008FU
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#define MSR_IA32_SMM_MONITOR_CTL 0x0000009BU
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#define MSR_IA32_PMC0 0x000000C1U
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#define MSR_IA32_PMC1 0x000000C2U
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#define MSR_IA32_PMC2 0x000000C3U
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#define MSR_IA32_PMC3 0x000000C4U
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#define MSR_IA32_PMC4 0x000000C5U
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#define MSR_IA32_PMC5 0x000000C6U
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#define MSR_IA32_PMC6 0x000000C7U
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#define MSR_IA32_PMC7 0x000000C8U
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/* Max. qualified performance clock counter */
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#define MSR_IA32_MPERF 0x000000E7U
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/* Actual performance clock counter */
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#define MSR_IA32_APERF 0x000000E8U
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#define MSR_IA32_MTRR_CAP 0x000000FEU
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#define MSR_IA32_ARCH_CAPABILITIES 0x0000010AU
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#define MSR_IA32_FLUSH_CMD 0x0000010BU
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#define MISC_FEATURE_ENABLES 0x00000140U
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#define MSR_IA32_SYSENTER_CS 0x00000174U
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#define MSR_IA32_SYSENTER_ESP 0x00000175U
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#define MSR_IA32_SYSENTER_EIP 0x00000176U
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#define MSR_IA32_MCG_CAP 0x00000179U
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#define MSR_IA32_MCG_STATUS 0x0000017AU
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#define MSR_IA32_MCG_CTL 0x0000017BU
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#define MSR_IA32_PERFEVTSEL0 0x00000186U
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#define MSR_IA32_PERFEVTSEL1 0x00000187U
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#define MSR_IA32_PERFEVTSEL2 0x00000188U
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#define MSR_IA32_PERFEVTSEL3 0x00000189U
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#define MSR_IA32_PERF_STATUS 0x00000198U
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#define MSR_IA32_PERF_CTL 0x00000199U
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#define MSR_IA32_CLOCK_MODULATION 0x0000019AU
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#define MSR_IA32_THERM_INTERRUPT 0x0000019BU
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#define MSR_IA32_THERM_STATUS 0x0000019CU
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#define MSR_IA32_MISC_ENABLE 0x000001A0U
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#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0U
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#define MSR_IA32_DEBUGCTL 0x000001D9U
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#define MSR_IA32_SMRR_PHYSBASE 0x000001F2U
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#define MSR_IA32_SMRR_PHYSMASK 0x000001F3U
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#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8U
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#define MSR_IA32_CPU_DCA_CAP 0x000001F9U
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#define MSR_IA32_DCA_0_CAP 0x000001FAU
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#define MSR_IA32_MTRR_PHYSBASE_0 0x00000200U
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#define MSR_IA32_MTRR_PHYSMASK_0 0x00000201U
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#define MSR_IA32_MTRR_PHYSBASE_1 0x00000202U
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#define MSR_IA32_MTRR_PHYSMASK_1 0x00000203U
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#define MSR_IA32_MTRR_PHYSBASE_2 0x00000204U
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#define MSR_IA32_MTRR_PHYSMASK_2 0x00000205U
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#define MSR_IA32_MTRR_PHYSBASE_3 0x00000206U
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#define MSR_IA32_MTRR_PHYSMASK_3 0x00000207U
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#define MSR_IA32_MTRR_PHYSBASE_4 0x00000208U
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#define MSR_IA32_MTRR_PHYSMASK_4 0x00000209U
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#define MSR_IA32_MTRR_PHYSBASE_5 0x0000020AU
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#define MSR_IA32_MTRR_PHYSMASK_5 0x0000020BU
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#define MSR_IA32_MTRR_PHYSBASE_6 0x0000020CU
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#define MSR_IA32_MTRR_PHYSMASK_6 0x0000020DU
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#define MSR_IA32_MTRR_PHYSBASE_7 0x0000020EU
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#define MSR_IA32_MTRR_PHYSMASK_7 0x0000020FU
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#define MSR_IA32_MTRR_PHYSBASE_8 0x00000210U
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#define MSR_IA32_MTRR_PHYSMASK_8 0x00000211U
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#define MSR_IA32_MTRR_PHYSBASE_9 0x00000212U
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#define MSR_IA32_MTRR_PHYSMASK_9 0x00000213U
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#define MSR_IA32_MTRR_FIX64K_00000 0x00000250U
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#define MSR_IA32_MTRR_FIX16K_80000 0x00000258U
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#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259U
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#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268U
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#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269U
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#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026AU
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#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026BU
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#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026CU
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#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026DU
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#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026EU
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#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026FU
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#define MSR_IA32_PAT 0x00000277U
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#define MSR_IA32_MC0_CTL2 0x00000280U
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#define MSR_IA32_MC1_CTL2 0x00000281U
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#define MSR_IA32_MC2_CTL2 0x00000282U
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#define MSR_IA32_MC3_CTL2 0x00000283U
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#define MSR_IA32_MC4_CTL2 0x00000284U
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#define MSR_IA32_MC5_CTL2 0x00000285U
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#define MSR_IA32_MC6_CTL2 0x00000286U
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#define MSR_IA32_MC7_CTL2 0x00000287U
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#define MSR_IA32_MC8_CTL2 0x00000288U
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#define MSR_IA32_MC9_CTL2 0x00000289U
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#define MSR_IA32_MC10_CTL2 0x0000028AU
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#define MSR_IA32_MC11_CTL2 0x0000028BU
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#define MSR_IA32_MC12_CTL2 0x0000028CU
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#define MSR_IA32_MC13_CTL2 0x0000028DU
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#define MSR_IA32_MC14_CTL2 0x0000028EU
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#define MSR_IA32_MC15_CTL2 0x0000028FU
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#define MSR_IA32_MC16_CTL2 0x00000290U
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#define MSR_IA32_MC17_CTL2 0x00000291U
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#define MSR_IA32_MC18_CTL2 0x00000292U
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#define MSR_IA32_MC19_CTL2 0x00000293U
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#define MSR_IA32_MC20_CTL2 0x00000294U
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#define MSR_IA32_MC21_CTL2 0x00000295U
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#define MSR_IA32_MTRR_DEF_TYPE 0x000002FFU
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#define MSR_SGXOWNEREPOCH0 0x00000300U
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#define MSR_SGXOWNEREPOCH1 0x00000301U
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#define MSR_IA32_FIXED_CTR0 0x00000309U
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#define MSR_IA32_FIXED_CTR1 0x0000030AU
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#define MSR_IA32_FIXED_CTR2 0x0000030BU
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#define MSR_IA32_PERF_CAPABILITIES 0x00000345U
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#define MSR_IA32_FIXED_CTR_CTL 0x0000038DU
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#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038EU
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#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038FU
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#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390U
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#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391U
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#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392U
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#define MSR_IA32_PEBS_ENABLE 0x000003F1U
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#define MSR_IA32_MC0_CTL 0x00000400U
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#define MSR_IA32_MC0_STATUS 0x00000401U
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#define MSR_IA32_MC0_ADDR 0x00000402U
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#define MSR_IA32_MC0_MISC 0x00000403U
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#define MSR_IA32_MC1_CTL 0x00000404U
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#define MSR_IA32_MC1_STATUS 0x00000405U
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#define MSR_IA32_MC1_ADDR 0x00000406U
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#define MSR_IA32_MC1_MISC 0x00000407U
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#define MSR_IA32_MC2_CTL 0x00000408U
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#define MSR_IA32_MC2_STATUS 0x00000409U
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#define MSR_IA32_MC2_ADDR 0x0000040AU
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#define MSR_IA32_MC2_MISC 0x0000040BU
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#define MSR_IA32_MC3_CTL 0x0000040CU
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#define MSR_IA32_MC3_STATUS 0x0000040DU
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#define MSR_IA32_MC3_ADDR 0x0000040EU
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#define MSR_IA32_MC3_MISC 0x0000040FU
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#define MSR_IA32_MC4_CTL 0x00000410U
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#define MSR_IA32_MC4_STATUS 0x00000411U
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#define MSR_IA32_MC4_ADDR 0x00000412U
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#define MSR_IA32_MC4_MISC 0x00000413U
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#define MSR_IA32_MC5_CTL 0x00000414U
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#define MSR_IA32_MC5_STATUS 0x00000415U
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#define MSR_IA32_MC5_ADDR 0x00000416U
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#define MSR_IA32_MC5_MISC 0x00000417U
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#define MSR_IA32_MC6_CTL 0x00000418U
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#define MSR_IA32_MC6_STATUS 0x00000419U
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#define MSR_IA32_MC6_ADDR 0x0000041AU
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#define MSR_IA32_MC6_MISC 0x0000041BU
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#define MSR_IA32_MC7_CTL 0x0000041CU
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#define MSR_IA32_MC7_STATUS 0x0000041DU
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#define MSR_IA32_MC7_ADDR 0x0000041EU
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#define MSR_IA32_MC7_MISC 0x0000041FU
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#define MSR_IA32_MC8_CTL 0x00000420U
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#define MSR_IA32_MC8_STATUS 0x00000421U
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#define MSR_IA32_MC8_ADDR 0x00000422U
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#define MSR_IA32_MC8_MISC 0x00000423U
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#define MSR_IA32_MC9_CTL 0x00000424U
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#define MSR_IA32_MC9_STATUS 0x00000425U
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#define MSR_IA32_MC9_ADDR 0x00000426U
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#define MSR_IA32_MC9_MISC 0x00000427U
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#define MSR_IA32_MC10_CTL 0x00000428U
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#define MSR_IA32_MC10_STATUS 0x00000429U
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#define MSR_IA32_MC10_ADDR 0x0000042AU
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#define MSR_IA32_MC10_MISC 0x0000042BU
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#define MSR_IA32_MC11_CTL 0x0000042CU
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#define MSR_IA32_MC11_STATUS 0x0000042DU
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#define MSR_IA32_MC11_ADDR 0x0000042EU
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#define MSR_IA32_MC11_MISC 0x0000042FU
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#define MSR_IA32_MC12_CTL 0x00000430U
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#define MSR_IA32_MC12_STATUS 0x00000431U
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#define MSR_IA32_MC12_ADDR 0x00000432U
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#define MSR_IA32_MC12_MISC 0x00000433U
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#define MSR_IA32_MC13_CTL 0x00000434U
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#define MSR_IA32_MC13_STATUS 0x00000435U
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#define MSR_IA32_MC13_ADDR 0x00000436U
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#define MSR_IA32_MC13_MISC 0x00000437U
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#define MSR_IA32_MC14_CTL 0x00000438U
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#define MSR_IA32_MC14_STATUS 0x00000439U
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#define MSR_IA32_MC14_ADDR 0x0000043AU
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#define MSR_IA32_MC14_MISC 0x0000043BU
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#define MSR_IA32_MC15_CTL 0x0000043CU
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#define MSR_IA32_MC15_STATUS 0x0000043DU
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#define MSR_IA32_MC15_ADDR 0x0000043EU
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#define MSR_IA32_MC15_MISC 0x0000043FU
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#define MSR_IA32_MC16_CTL 0x00000440U
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#define MSR_IA32_MC16_STATUS 0x00000441U
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#define MSR_IA32_MC16_ADDR 0x00000442U
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#define MSR_IA32_MC16_MISC 0x00000443U
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#define MSR_IA32_MC17_CTL 0x00000444U
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#define MSR_IA32_MC17_STATUS 0x00000445U
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#define MSR_IA32_MC17_ADDR 0x00000446U
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#define MSR_IA32_MC17_MISC 0x00000447U
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#define MSR_IA32_MC18_CTL 0x00000448U
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#define MSR_IA32_MC18_STATUS 0x00000449U
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#define MSR_IA32_MC18_ADDR 0x0000044AU
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#define MSR_IA32_MC18_MISC 0x0000044BU
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#define MSR_IA32_MC19_CTL 0x0000044CU
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#define MSR_IA32_MC19_STATUS 0x0000044DU
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#define MSR_IA32_MC19_ADDR 0x0000044EU
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#define MSR_IA32_MC19_MISC 0x0000044FU
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#define MSR_IA32_MC20_CTL 0x00000450U
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#define MSR_IA32_MC20_STATUS 0x00000451U
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#define MSR_IA32_MC20_ADDR 0x00000452U
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#define MSR_IA32_MC20_MISC 0x00000453U
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#define MSR_IA32_MC21_CTL 0x00000454U
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#define MSR_IA32_MC21_STATUS 0x00000455U
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#define MSR_IA32_MC21_ADDR 0x00000456U
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#define MSR_IA32_MC21_MISC 0x00000457U
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#define MSR_IA32_VMX_BASIC 0x00000480U
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#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481U
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#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482U
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#define MSR_IA32_VMX_EXIT_CTLS 0x00000483U
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#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484U
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#define MSR_IA32_VMX_MISC 0x00000485U
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#define MSR_IA32_VMX_CR0_FIXED0 0x00000486U
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#define MSR_IA32_VMX_CR0_FIXED1 0x00000487U
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#define MSR_IA32_VMX_CR4_FIXED0 0x00000488U
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#define MSR_IA32_VMX_CR4_FIXED1 0x00000489U
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#define MSR_IA32_VMX_VMCS_ENUM 0x0000048AU
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#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048BU
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#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048CU
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#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048DU
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#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048EU
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#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048FU
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#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490U
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#define MSR_IA32_VMX_VMFUNC 0x00000491U
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#define MSR_IA32_A_PMC0 0x000004C1U
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#define MSR_IA32_A_PMC1 0x000004C2U
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#define MSR_IA32_A_PMC2 0x000004C3U
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#define MSR_IA32_A_PMC3 0x000004C4U
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#define MSR_IA32_A_PMC4 0x000004C5U
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#define MSR_IA32_A_PMC5 0x000004C6U
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#define MSR_IA32_A_PMC6 0x000004C7U
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#define MSR_IA32_A_PMC7 0x000004C8U
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#define MSR_IA32_SGX_SVN_STATUS 0x00000500U
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#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560U
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#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561U
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#define MSR_IA32_RTIT_CTL 0x00000570U
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#define MSR_IA32_RTIT_STATUS 0x00000571U
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#define MSR_IA32_RTIT_CR3_MATCH 0x00000572U
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#define MSR_IA32_RTIT_ADDR0_A 0x00000580U
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#define MSR_IA32_RTIT_ADDR0_B 0x00000581U
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#define MSR_IA32_RTIT_ADDR1_A 0x00000582U
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#define MSR_IA32_RTIT_ADDR1_B 0x00000583U
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#define MSR_IA32_RTIT_ADDR2_A 0x00000584U
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#define MSR_IA32_RTIT_ADDR2_B 0x00000585U
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#define MSR_IA32_RTIT_ADDR3_A 0x00000586U
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#define MSR_IA32_RTIT_ADDR3_B 0x00000587U
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#define MSR_IA32_DS_AREA 0x00000600U
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#define MSR_IA32_TSC_DEADLINE 0x000006E0U
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#define MSR_IA32_PM_ENABLE 0x00000770U
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#define MSR_IA32_HWP_CAPABILITIES 0x00000771U
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#define MSR_IA32_HWP_REQUEST_PKG 0x00000772U
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#define MSR_IA32_HWP_INTERRUPT 0x00000773U
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#define MSR_IA32_HWP_REQUEST 0x00000774U
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#define MSR_IA32_HWP_PECI_REQUEST_INFO 0x00000775U
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#define MSR_IA32_HWP_STATUS 0x00000777U
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#define MSR_IA32_EXT_XAPICID 0x00000802U
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#define MSR_IA32_EXT_APIC_VERSION 0x00000803U
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#define MSR_IA32_EXT_APIC_TPR 0x00000808U
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#define MSR_IA32_EXT_APIC_PPR 0x0000080AU
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#define MSR_IA32_EXT_APIC_EOI 0x0000080BU
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#define MSR_IA32_EXT_APIC_LDR 0x0000080DU
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#define MSR_IA32_EXT_APIC_SIVR 0x0000080FU
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#define MSR_IA32_EXT_APIC_ISR0 0x00000810U
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#define MSR_IA32_EXT_APIC_ISR1 0x00000811U
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#define MSR_IA32_EXT_APIC_ISR2 0x00000812U
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#define MSR_IA32_EXT_APIC_ISR3 0x00000813U
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#define MSR_IA32_EXT_APIC_ISR4 0x00000814U
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#define MSR_IA32_EXT_APIC_ISR5 0x00000815U
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#define MSR_IA32_EXT_APIC_ISR6 0x00000816U
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#define MSR_IA32_EXT_APIC_ISR7 0x00000817U
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#define MSR_IA32_EXT_APIC_TMR0 0x00000818U
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#define MSR_IA32_EXT_APIC_TMR1 0x00000819U
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#define MSR_IA32_EXT_APIC_TMR2 0x0000081AU
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#define MSR_IA32_EXT_APIC_TMR3 0x0000081BU
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#define MSR_IA32_EXT_APIC_TMR4 0x0000081CU
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#define MSR_IA32_EXT_APIC_TMR5 0x0000081DU
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#define MSR_IA32_EXT_APIC_TMR6 0x0000081EU
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#define MSR_IA32_EXT_APIC_TMR7 0x0000081FU
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#define MSR_IA32_EXT_APIC_IRR0 0x00000820U
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#define MSR_IA32_EXT_APIC_IRR1 0x00000821U
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#define MSR_IA32_EXT_APIC_IRR2 0x00000822U
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#define MSR_IA32_EXT_APIC_IRR3 0x00000823U
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#define MSR_IA32_EXT_APIC_IRR4 0x00000824U
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#define MSR_IA32_EXT_APIC_IRR5 0x00000825U
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#define MSR_IA32_EXT_APIC_IRR6 0x00000826U
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#define MSR_IA32_EXT_APIC_IRR7 0x00000827U
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#define MSR_IA32_EXT_APIC_ESR 0x00000828U
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#define MSR_IA32_EXT_APIC_LVT_CMCI 0x0000082FU
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#define MSR_IA32_EXT_APIC_ICR 0x00000830U
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#define MSR_IA32_EXT_APIC_LVT_TIMER 0x00000832U
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#define MSR_IA32_EXT_APIC_LVT_THERMAL 0x00000833U
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#define MSR_IA32_EXT_APIC_LVT_PMI 0x00000834U
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#define MSR_IA32_EXT_APIC_LVT_LINT0 0x00000835U
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#define MSR_IA32_EXT_APIC_LVT_LINT1 0x00000836U
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#define MSR_IA32_EXT_APIC_LVT_ERROR 0x00000837U
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#define MSR_IA32_EXT_APIC_INIT_COUNT 0x00000838U
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#define MSR_IA32_EXT_APIC_CUR_COUNT 0x00000839U
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#define MSR_IA32_EXT_APIC_DIV_CONF 0x0000083EU
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#define MSR_IA32_EXT_APIC_SELF_IPI 0x0000083FU
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#define MSR_IA32_DEBUG_INTERFACE 0x00000C80U
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#define MSR_IA32_L3_QOS_CFG 0x00000C81U
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#define MSR_IA32_L2_QOS_CFG 0x00000C82U
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#define MSR_IA32_QM_EVTSEL 0x00000C8DU
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#define MSR_IA32_QM_CTR 0x00000C8EU
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#define MSR_IA32_PQR_ASSOC 0x00000C8FU
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#define MSR_IA32_L3_MASK_0 0x00000C90U
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#define MSR_IA32_L2_MASK_0 0x00000D10U
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#define MSR_IA32_BNDCFGS 0x00000D90U
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#define MSR_IA32_EFER 0xC0000080U
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#define MSR_IA32_STAR 0xC0000081U
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#define MSR_IA32_LSTAR 0xC0000082U
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#define MSR_IA32_FMASK 0xC0000084U
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#define MSR_IA32_FS_BASE 0xC0000100U
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#define MSR_IA32_GS_BASE 0xC0000101U
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#define MSR_IA32_KERNEL_GS_BASE 0xC0000102U
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#define MSR_IA32_TSC_AUX 0xC0000103U
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/* ATOM specific MSRs */
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#define MSR_ATOM_EBL_CR_POWERON 0x0000002AU
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#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040U
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#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041U
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#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042U
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#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043U
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#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044U
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#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045U
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#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046U
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#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047U
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#define MSR_ATOM_LASTBRANCH_0_TO_LIP 0x00000060U
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#define MSR_ATOM_LASTBRANCH_1_TO_LIP 0x00000061U
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#define MSR_ATOM_LASTBRANCH_2_TO_LIP 0x00000062U
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#define MSR_ATOM_LASTBRANCH_3_TO_LIP 0x00000063U
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#define MSR_ATOM_LASTBRANCH_4_TO_LIP 0x00000064U
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#define MSR_ATOM_LASTBRANCH_5_TO_LIP 0x00000065U
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#define MSR_ATOM_LASTBRANCH_6_TO_LIP 0x00000066U
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#define MSR_ATOM_LASTBRANCH_7_TO_LIP 0x00000067U
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/* Scalable bus speed */
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#define MSR_ATOM_FSB_FREQ 0x000000CDU
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#define MSR_PLATFORM_INFO 0x000000CEU
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/* L2 hardware enabled */
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#define MSR_ATOM_BBL_CR_CTL3 0x0000011EU
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#define MSR_ATOM_THERM2_CTL 0x0000019DU
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#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9U
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#define MSR_ATOM_LER_FROM_LIP 0x000001DDU
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#define MSR_ATOM_LER_TO_LIP 0x000001DEU
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#ifdef PROFILING_ON
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/* Core (and Goldmont) specific MSRs */
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#define MSR_CORE_LASTBRANCH_TOS 0x000001C9U
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/* Last branch record stack TOS */
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#define MSR_CORE_LASTBRANCH_0_FROM_IP 0x00000680U
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/* Last branch record 0 from IP */
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#define MSR_CORE_LASTBRANCH_0_TO_IP 0x000006C0U
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/* Last branch record 0 to IP */
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#endif
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/* LINCROFT specific MSRs */
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#define MSR_LNC_BIOS_CACHE_AS_RAM 0x000002E0U /* Configure CAR */
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/* EFER bits */
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#define MSR_IA32_EFER_SCE_BIT (1UL << 0U)
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#define MSR_IA32_EFER_LME_BIT (1UL << 8U) /* IA32e mode enable */
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#define MSR_IA32_EFER_LMA_BIT (1UL << 10U) /* IA32e mode active */
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#define MSR_IA32_EFER_NXE_BIT (1UL << 11U)
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/* FEATURE CONTROL bits */
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#define MSR_IA32_FEATURE_CONTROL_LOCK (1U << 0U)
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#define MSR_IA32_FEATURE_CONTROL_VMX_SMX (1U << 1U)
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#define MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX (1U << 2U)
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#define MSR_IA32_FEATURE_CONTROL_SENTERS_MSK (0x7F00U)
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#define MSR_IA32_FEATURE_CONTROL_SENTER (1U << 15U)
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#define MSR_IA32_FEATURE_CONTROL_SGX_LC (1U << 17U)
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#define MSR_IA32_FEATURE_CONTROL_SGX_GE (1U << 18U)
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/* PAT memory type definitions */
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#define PAT_MEM_TYPE_UC 0x00UL /* uncached */
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#define PAT_MEM_TYPE_WC 0x01UL /* write combining */
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#define PAT_MEM_TYPE_WT 0x04UL /* write through */
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#define PAT_MEM_TYPE_WP 0x05UL /* write protected */
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#define PAT_MEM_TYPE_WB 0x06UL /* writeback */
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#define PAT_MEM_TYPE_UCM 0x07UL /* uncached minus */
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#ifndef ASSEMBLER
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static inline bool pat_mem_type_invalid(uint64_t x)
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{
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return ((x & ~0x7UL) != 0UL || (x & 0x6UL) == 0x2UL);
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}
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static inline bool is_x2apic_msr(uint32_t msr)
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{
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bool ret = false;
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/*
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* if msr is in the range of x2APIC MSRs
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*/
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if ((msr >= MSR_IA32_EXT_XAPICID) && (msr <= MSR_IA32_EXT_APIC_SELF_IPI)) {
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ret = true;
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}
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return ret;
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}
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static inline bool is_x2apic_read_only_msr(uint32_t msr)
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{
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bool ret = false;
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if ((msr == MSR_IA32_EXT_XAPICID) ||
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(msr == MSR_IA32_EXT_APIC_VERSION) ||
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(msr == MSR_IA32_EXT_APIC_PPR) ||
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(msr == MSR_IA32_EXT_APIC_LDR) ||
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((msr >= MSR_IA32_EXT_APIC_ISR0) &&
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(msr <= MSR_IA32_EXT_APIC_IRR7)) ||
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(msr == MSR_IA32_EXT_APIC_CUR_COUNT)) {
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ret = true;
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}
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return ret;
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}
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|
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static inline bool is_x2apic_write_only_msr(uint32_t msr)
|
|
{
|
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bool ret = false;
|
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if ((msr == MSR_IA32_EXT_APIC_EOI) || (msr == MSR_IA32_EXT_APIC_SELF_IPI)) {
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ret = true;
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}
|
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return ret;
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}
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#endif /* ASSEMBLER */
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|
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/* 5 high-order bits in every field are reserved */
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#define PAT_FIELD_RSV_BITS (0xF8U)
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|
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#define PAT_POWER_ON_VALUE (PAT_MEM_TYPE_WB + \
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(PAT_MEM_TYPE_WT << 8U) + \
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(PAT_MEM_TYPE_UCM << 16U) + \
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(PAT_MEM_TYPE_UC << 24U) + \
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(PAT_MEM_TYPE_WB << 32U) + \
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(PAT_MEM_TYPE_WT << 40U) + \
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(PAT_MEM_TYPE_UCM << 48U) + \
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(PAT_MEM_TYPE_UC << 56U))
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|
|
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#define PAT_ALL_UC_VALUE (PAT_MEM_TYPE_UC + \
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(PAT_MEM_TYPE_UC << 8U) + \
|
|
(PAT_MEM_TYPE_UC << 16U) + \
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(PAT_MEM_TYPE_UC << 24U) + \
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(PAT_MEM_TYPE_UC << 32U) + \
|
|
(PAT_MEM_TYPE_UC << 40U) + \
|
|
(PAT_MEM_TYPE_UC << 48U) + \
|
|
(PAT_MEM_TYPE_UC << 56U))
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|
|
|
/* MTRR memory type definitions */
|
|
#define MTRR_MEM_TYPE_UC 0x00UL /* uncached */
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|
#define MTRR_MEM_TYPE_WC 0x01UL /* write combining */
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#define MTRR_MEM_TYPE_WT 0x04UL /* write through */
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#define MTRR_MEM_TYPE_WP 0x05UL /* write protected */
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#define MTRR_MEM_TYPE_WB 0x06UL /* writeback */
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|
|
|
/* misc. MTRR flag definitions */
|
|
#define MTRR_ENABLE 0x800U /* MTRR enable */
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|
#define MTRR_FIX_ENABLE 0x400U /* fixed range MTRR enable */
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|
#define MTRR_VALID 0x800U /* MTRR setting is valid */
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|
|
|
/* SPEC & PRED bit */
|
|
#define SPEC_ENABLE_IBRS (1U << 0U)
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|
#define SPEC_ENABLE_STIBP (1U << 1U)
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|
#define PRED_SET_IBPB (1U << 0U)
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|
|
|
/* IA32 ARCH Capabilities bit */
|
|
#define IA32_ARCH_CAP_RDCL_NO (1U << 0U)
|
|
#define IA32_ARCH_CAP_IBRS_ALL (1U << 1U)
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|
#define IA32_ARCH_CAP_RSBA (1U << 2U)
|
|
#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3U)
|
|
#define IA32_ARCH_CAP_SSB_NO (1U << 4U)
|
|
|
|
/* Flush L1 D-cache */
|
|
#define IA32_L1D_FLUSH (1UL << 0U)
|
|
|
|
/* MSR_IA32_MISC_ENABLE */
|
|
#define MISC_ENABLE_FAST_STRING (1U << 0U)
|
|
#define MISC_ENABLE_TCC (1U << 3U)
|
|
#define MISC_ENABLE_PMA (1U << 7U)
|
|
#define MISC_ENABLE_BTS_UNAVAIL (1U << 11U)
|
|
#define MISC_ENABLE_PEBS_UNAVAIL (1U << 12U)
|
|
#define MISC_ENABLE_TM2_ENABLE (1U << 13U)
|
|
#define MISC_ENABLE_EITS (1U << 16U)
|
|
#define MISC_ENABLE_MONITOR_ENA (1U << 18U)
|
|
#define MISC_ENABLE_LIMIT_CPUID (1U << 22U)
|
|
#define MISC_ENABLE_xTPR (1U << 23U)
|
|
#define MISC_ENABLE_XD (1U << 34U)
|
|
|
|
#endif /* MSR_H */
|