mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-04 06:26:54 +00:00
e1564edda5
This patch fixes the following violations: 1. Implicit conversion: actual to formal param 2. Value is not of appropriate type 3. No cast for widening complex int expression 4. Widening cast on complex integer expression 5. Narrower int conversion without cast. Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
632 lines
14 KiB
C
632 lines
14 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VTD_H
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#define VTD_H
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/*
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* Intel IOMMU register specification per version 1.0 public spec.
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*/
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#define DMAR_VER_REG 0x0U /* Arch version supported by this IOMMU */
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#define DMAR_CAP_REG 0x8U /* Hardware supported capabilities */
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#define DMAR_ECAP_REG 0x10U /* Extended capabilities supported */
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#define DMAR_GCMD_REG 0x18U /* Global command register */
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#define DMAR_GSTS_REG 0x1cU /* Global status register */
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#define DMAR_RTADDR_REG 0x20U /* Root entry table */
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#define DMAR_CCMD_REG 0x28U /* Context command reg */
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#define DMAR_FSTS_REG 0x34U /* Fault Status register */
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#define DMAR_FECTL_REG 0x38U /* Fault control register */
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#define DMAR_FEDATA_REG 0x3cU /* Fault event interrupt data register */
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#define DMAR_FEADDR_REG 0x40U /* Fault event interrupt addr register */
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#define DMAR_FEUADDR_REG 0x44U /* Upper address register */
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#define DMAR_AFLOG_REG 0x58U /* Advanced Fault control */
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#define DMAR_PMEN_REG 0x64U /* Enable Protected Memory Region */
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#define DMAR_PLMBASE_REG 0x68U /* PMRR Low addr */
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#define DMAR_PLMLIMIT_REG 0x6cU /* PMRR low limit */
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#define DMAR_PHMBASE_REG 0x70U /* pmrr high base addr */
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#define DMAR_PHMLIMIT_REG 0x78U /* pmrr high limit */
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#define DMAR_IQH_REG 0x80U /* Invalidation queue head register */
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#define DMAR_IQT_REG 0x88U /* Invalidation queue tail register */
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#define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
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#define DMAR_IQA_REG 0x90U /* Invalidation queue addr register */
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#define DMAR_ICS_REG 0x9cU /* Invalidation complete status register */
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#define DMAR_IRTA_REG 0xb8U /* Interrupt remapping table addr register */
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static inline uint8_t dmar_ver_major(uint64_t version)
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{
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return (((uint8_t)version & 0xf0U) >> 4U);
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}
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static inline uint8_t dmar_ver_minor(uint64_t version)
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{
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return ((uint8_t)version & 0x0fU);
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}
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/*
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* Decoding Capability Register
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*/
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static inline uint8_t iommu_cap_pi(uint64_t cap)
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{
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return ((uint8_t)(cap >> 59U) & 1U);
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}
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static inline uint8_t iommu_cap_read_drain(uint64_t cap)
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{
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return ((uint8_t)(cap >> 55U) & 1U);
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}
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static inline uint8_t iommu_cap_write_drain(uint64_t cap)
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{
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return ((uint8_t)(cap >> 54U) & 1U);
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}
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static inline uint8_t iommu_cap_max_amask_val(uint64_t cap)
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{
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return ((uint8_t)(cap >> 48U) & 0x3fU);
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}
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static inline uint16_t iommu_cap_num_fault_regs(uint64_t cap)
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{
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return (((uint16_t)(cap >> 40U) & 0xffU) + 1U);
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}
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static inline uint8_t iommu_cap_pgsel_inv(uint64_t cap)
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{
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return ((uint8_t)(cap >> 39U) & 1U);
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}
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static inline uint8_t iommu_cap_super_page_val(uint64_t cap)
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{
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return ((uint8_t)(cap >> 34U) & 0xfU);
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}
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static inline uint16_t iommu_cap_fault_reg_offset(uint64_t cap)
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{
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return (((uint16_t)(cap >> 24U) & 0x3ffU) * 16U);
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}
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static inline uint16_t iommu_cap_max_fault_reg_offset(uint64_t cap)
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{
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return (iommu_cap_fault_reg_offset(cap) +
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(iommu_cap_num_fault_regs(cap) * 16U));
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}
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static inline uint8_t iommu_cap_zlr(uint64_t cap)
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{
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return ((uint8_t)(cap >> 22U) & 1U);
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}
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static inline uint8_t iommu_cap_isoch(uint64_t cap)
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{
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return ((uint8_t)(cap >> 23U) & 1U);
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}
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static inline uint8_t iommu_cap_mgaw(uint64_t cap)
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{
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return (((uint8_t)(cap >> 16U) & 0x3fU) + 1U);
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}
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static inline uint8_t iommu_cap_sagaw(uint64_t cap)
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{
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return ((uint8_t)(cap >> 8U) & 0x1fU);
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}
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static inline uint8_t iommu_cap_caching_mode(uint64_t cap)
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{
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return ((uint8_t)(cap >> 7U) & 1U);
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}
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static inline uint8_t iommu_cap_phmr(uint64_t cap)
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{
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return ((uint8_t)(cap >> 6U) & 1U);
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}
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static inline uint8_t iommu_cap_plmr(uint64_t cap)
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{
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return ((uint8_t)(cap >> 5U) & 1U);
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}
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static inline uint8_t iommu_cap_rwbf(uint64_t cap)
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{
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return ((uint8_t)(cap >> 4U) & 1U);
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}
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static inline uint8_t iommu_cap_afl(uint64_t cap)
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{
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return ((uint8_t)(cap >> 3U) & 1U);
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}
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static inline uint32_t iommu_cap_ndoms(uint64_t cap)
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{
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return ((1U) << (4U + (2U * ((uint8_t)cap & 0x7U))));
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}
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/*
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* Decoding Extended Capability Register
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*/
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static inline uint8_t iommu_ecap_c(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 0U) & 1U);
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}
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static inline uint8_t iommu_ecap_qi(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 1U) & 1U);
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}
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static inline uint8_t iommu_ecap_dt(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 2U) & 1U);
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}
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static inline uint8_t iommu_ecap_ir(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 3U) & 1U);
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}
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static inline uint8_t iommu_ecap_eim(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 4U) & 1U);
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}
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static inline uint8_t iommu_ecap_pt(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 6U) & 1U);
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}
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static inline uint8_t iommu_ecap_sc(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 7U) & 1U);
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}
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static inline uint16_t iommu_ecap_iro(uint64_t ecap)
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{
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return ((uint16_t)(ecap >> 8U) & 0x3ffU);
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}
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static inline uint8_t iommu_ecap_mhmv(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 20U) & 0xfU);
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}
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static inline uint8_t iommu_ecap_ecs(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 24U) & 1U);
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}
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static inline uint8_t iommu_ecap_mts(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 25U) & 1U);
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}
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static inline uint8_t iommu_ecap_nest(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 26U) & 1U);
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}
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static inline uint8_t iommu_ecap_dis(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 27U) & 1U);
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}
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static inline uint8_t iommu_ecap_prs(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 29U) & 1U);
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}
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static inline uint8_t iommu_ecap_ers(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 30U) & 1U);
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}
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static inline uint8_t iommu_ecap_srs(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 31U) & 1U);
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}
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static inline uint8_t iommu_ecap_nwfs(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 33U) & 1U);
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}
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static inline uint8_t iommu_ecap_eafs(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 34U) & 1U);
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}
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static inline uint8_t iommu_ecap_pss(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 35U) & 0x1fU);
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}
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static inline uint8_t iommu_ecap_pasid(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 40U) & 1U);
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}
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static inline uint8_t iommu_ecap_dit(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 41U) & 1U);
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}
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static inline uint8_t iommu_ecap_pds(uint64_t ecap)
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{
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return ((uint8_t)(ecap >> 42U) & 1U);
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}
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/* PMEN_REG */
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#define DMA_PMEN_EPM (1U << 31U)
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#define DMA_PMEN_PRS (1U << 0U)
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/* GCMD_REG */
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#define DMA_GCMD_TE (1U << 31U)
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#define DMA_GCMD_SRTP (1U << 30U)
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#define DMA_GCMD_SFL (1U << 29U)
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#define DMA_GCMD_EAFL (1U << 28U)
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#define DMA_GCMD_WBF (1U << 27U)
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#define DMA_GCMD_QIE (1U << 26U)
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#define DMA_GCMD_SIRTP (1U << 24U)
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#define DMA_GCMD_IRE (1U << 25U)
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#define DMA_GCMD_CFI (1U << 23U)
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/* GSTS_REG */
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#define DMA_GSTS_TES (1U << 31U)
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#define DMA_GSTS_RTPS (1U << 30U)
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#define DMA_GSTS_FLS (1U << 29U)
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#define DMA_GSTS_AFLS (1U << 28U)
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#define DMA_GSTS_WBFS (1U << 27U)
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#define DMA_GSTS_QIES (1U << 26U)
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#define DMA_GSTS_IRTPS (1U << 24U)
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#define DMA_GSTS_IRES (1U << 25U)
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#define DMA_GSTS_CFIS (1U << 23U)
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/* CCMD_REG */
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#define DMA_CCMD_ICC (1UL << 63U)
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#define DMA_CCMD_ICC_32 (1U << 31U)
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#define DMA_CCMD_GLOBAL_INVL (1UL << 61U)
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#define DMA_CCMD_DOMAIN_INVL (2UL << 61U)
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#define DMA_CCMD_DEVICE_INVL (3UL << 61U)
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static inline uint64_t dma_ccmd_fm(uint8_t fm)
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{
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return (((uint64_t)fm & 0x3UL) << 32UL);
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}
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#define DMA_CCMD_MASK_NOBIT 0UL
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#define DMA_CCMD_MASK_1BIT 1UL
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#define DMA_CCMD_MASK_2BIT 2UL
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#define DMA_CCMD_MASK_3BIT 3UL
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static inline uint64_t dma_ccmd_sid(uint16_t sid)
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{
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return (((uint64_t)sid & 0xffffUL) << 16UL);
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}
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static inline uint16_t dma_ccmd_did(uint16_t did)
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{
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return (did & 0xffffU);
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}
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static inline uint8_t dma_ccmd_get_caig_32(uint32_t gaig)
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{
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return ((uint8_t)(gaig >> 27U) & 0x3U);
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}
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/* IOTLB_REG */
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#define DMA_IOTLB_IVT (((uint64_t)1UL) << 63U)
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#define DMA_IOTLB_IVT_32 (((uint32_t)1U) << 31U)
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#define DMA_IOTLB_GLOBAL_INVL (((uint64_t)1UL) << 60U)
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#define DMA_IOTLB_DOMAIN_INVL (((uint64_t)2UL) << 60U)
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#define DMA_IOTLB_PAGE_INVL (((uint64_t)3UL) << 60U)
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#define DMA_IOTLB_DR (((uint64_t)1UL) << 49U)
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#define DMA_IOTLB_DW (((uint64_t)1UL) << 48U)
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static inline uint64_t dma_iotlb_did(uint16_t did)
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{
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return (((uint64_t)did & 0xffffUL) << 32UL);
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}
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static inline uint8_t dma_iotlb_get_iaig_32(uint32_t iai)
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{
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return ((uint8_t)(iai >> 25U) & 0x3U);
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}
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/* INVALIDATE_ADDRESS_REG */
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static inline uint8_t dma_iotlb_invl_addr_am(uint8_t am)
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{
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return (am & 0x3fU);
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}
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#define DMA_IOTLB_INVL_ADDR_IH_UNMODIFIED (((uint64_t)1UL) << 6U)
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/* FECTL_REG */
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#define DMA_FECTL_IM (((uint32_t)1U) << 31U)
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/* FSTS_REG */
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static inline bool dma_fsts_pfo(uint32_t pfo)
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{
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return (((pfo >> 0U) & 1U) == 1U);
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}
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static inline bool dma_fsts_ppf(uint32_t ppf)
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{
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return (((ppf >> 1U) & 1U) == 1U);
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}
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static inline bool dma_fsts_afo(uint32_t afo)
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{
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return (((afo >> 2U) & 1U) == 1U);
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}
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static inline bool dma_fsts_apf(uint32_t apf)
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{
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return (((apf >> 3U) & 1U) == 1U);
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}
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static inline bool dma_fsts_iqe(uint32_t iqe)
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{
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return (((iqe >> 4U) & 1U) == 1U);
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}
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static inline bool dma_fsts_ice(uint32_t ice)
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{
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return (((ice >> 5U) & 1U) == 1U);
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}
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static inline bool dma_fsts_ite(uint32_t ite)
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{
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return (((ite >> 6U) & 1U) == 1U);
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}
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static inline bool dma_fsts_pro(uint32_t pro)
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{
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return (((pro >> 7U) & 1U) == 1U);
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}
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static inline uint8_t dma_fsts_fri(uint32_t fri)
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{
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return ((uint8_t)(fri >> 8U) & 0xFFU);
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}
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/* FRCD_REGs: upper 64 bits*/
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static inline bool dma_frcd_up_f(uint64_t up_f)
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{
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return (((up_f >> 63U) & 1UL) == 1UL);
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}
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static inline uint8_t dma_frcd_up_t(uint64_t up_t)
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{
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return ((uint8_t)(up_t >> 62U) & 1U);
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}
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static inline uint8_t dma_frcd_up_at(uint64_t up_at)
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{
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return ((uint8_t)(up_at >> 60U) & 3U);
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}
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static inline uint32_t dma_frcd_up_pasid(uint64_t up_pasid)
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{
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return ((uint32_t)(up_pasid >> 40U) & 0xfffffU);
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}
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static inline uint8_t dma_frcd_up_fr(uint64_t up_fr)
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{
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return ((uint8_t)(up_fr >> 32U) & 0xffU);
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}
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static inline bool dma_frcd_up_pp(uint64_t up_pp)
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{
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return (((up_pp >> 31U) & 1UL) == 1UL);
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}
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static inline bool dma_frcd_up_exe(uint64_t up_exe)
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{
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return (((up_exe >> 30U) & 1UL) == 1UL);
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}
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static inline bool dma_frcd_up_priv(uint64_t up_priv)
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{
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return (((up_priv >> 29U) & 1UL) == 1UL);
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}
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static inline uint16_t dma_frcd_up_sid(uint64_t up_sid)
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{
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return ((uint16_t)up_sid & 0xffffU);
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}
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#define DMAR_CONTEXT_TRANSLATION_TYPE_TRANSLATED 0x00U
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#define DMAR_CONTEXT_TRANSLATION_TYPE_RESERVED 0x01U
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#define DMAR_CONTEXT_TRANSLATION_TYPE_PASSED_THROUGH 0x02U
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#define DRHD_FLAG_INCLUDE_PCI_ALL_MASK (1U)
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#define DEVFUN(dev, fun) (((dev & 0x1FU) << 3U) | ((fun & 0x7U)))
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struct dmar_dev_scope {
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uint8_t bus;
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uint8_t devfun;
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};
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struct dmar_drhd {
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uint32_t dev_cnt;
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uint16_t segment;
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uint8_t flags;
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bool ignore;
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uint64_t reg_base_addr;
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/* assume no pci device hotplug support */
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struct dmar_dev_scope *devices;
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};
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struct dmar_info {
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uint32_t drhd_count;
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struct dmar_drhd *drhd_units;
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};
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extern struct dmar_info *get_dmar_info(void);
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/**
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* @file vtd.h
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*
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* @brief public APIs for VT-d
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*/
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/**
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* @brief VT-d
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*
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* @defgroup acrn_vtd ACRN VT-d
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* @{
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*/
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/**
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* @brief iommu domain.
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*
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* This struct declaration for iommu domain.
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*
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*/
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struct iommu_domain;
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/**
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* @brief Assign a device specified by bus & devfun to a iommu domain.
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*
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* Remove the device from the VM0 domain (if present), and add it to the specific domain.
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*
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* @param[in] domain iommu domain the device is assigned to
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* @param[in] bus the 8-bit bus number of the device
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* @param[in] devfun the 8-bit device(5-bit):function(3-bit) of the device
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*
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* @retval 0 on success.
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* @retval 1 fail to unassign the device
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*
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* @pre domain != NULL
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*
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*/
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int assign_iommu_device(struct iommu_domain *domain, uint8_t bus, uint8_t devfun);
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/**
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* @brief Unassign a device specified by bus & devfun from a iommu domain .
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*
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* Remove the device from the specific domain, and then add it to the VM0 domain (if present).
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*
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* @param[in] domain iommu domain the device is assigned to
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* @param[in] bus the 8-bit bus number of the device
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* @param[in] devfun the 8-bit device(5-bit):function(3-bit) of the device
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*
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* @retval 0 on success.
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* @retval 1 fail to unassign the device
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*
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* @pre domain != NULL
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*
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*/
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int unassign_iommu_device(const struct iommu_domain *domain, uint8_t bus, uint8_t devfun);
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/**
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* @brief Create a iommu domain for a VM specified by vm_id.
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*
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* Create a iommu domain for a VM specified by vm_id, along with address translation table and address width.
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*
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* @param[in] vm_id vm_id of the VM the domain created for
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* @param[in] translation_table the physcial address of EPT table of the VM specified by the vm_id
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* @param[in] addr_width address width of the VM
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*
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* @return Pointer to the created iommu_domain
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*
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* @retval NULL when \p translation_table is 0
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* @retval !NULL when \p translation_table is not 0
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*
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* @pre vm_id is valid
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* @pre translation_table != 0
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*
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*/
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struct iommu_domain *create_iommu_domain(uint16_t vm_id, uint64_t translation_table, uint32_t addr_width);
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/**
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* @brief Destroy the specific iommu domain.
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*
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* Destroy the specific iommu domain when a VM no longer needs it.
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*
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* @param[in] domain iommu domain to destroy
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*
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* @pre domain != NULL
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*
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*/
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void destroy_iommu_domain(struct iommu_domain *domain);
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/**
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* @brief Enable translation of IOMMUs.
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*
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* Enable address translation of all IOMMUs, which are not ignored on the platform.
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*
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*/
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void enable_iommu(void);
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/**
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* @brief Disable translation of IOMMUs.
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*
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* Disable address translation of all IOMMUs, which are not ignored on the platform.
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*
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*/
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void disable_iommu(void);
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/**
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* @brief Suspend IOMMUs.
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*
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* Suspend all IOMMUs, which are not ignored on the platform.
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*
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*/
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void suspend_iommu(void);
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/**
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* @brief Resume IOMMUs.
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*
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* Resume all IOMMUs, which are not ignored on the platform.
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*
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*/
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void resume_iommu(void);
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/**
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* @brief Init IOMMUs.
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*
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* Register DMAR units on the platform according to the pre-parsed information
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* or DMAR table. IOMMU is a must have feature, if init_iommu failed, the system
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* should not continue booting.
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*
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* @retval 0 on success
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* @retval <0 on failure
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*
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*/
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int init_iommu(void);
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/**
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* @brief Init VM0 domain of iommu.
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*
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* Create VM0 domain using the Normal World's EPT table of VM0 as address translation table.
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* All PCI devices are added to the VM0 domain when creating it.
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*
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* @param[in] vm0 pointer to VM0
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*
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* @pre vm0 shall point to VM0
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*
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* @remark to reduce boot time & memory cost, a config IOMMU_INIT_BUS_LIMIT, which limit the bus number.
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*
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*/
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void init_iommu_vm0_domain(struct acrn_vm *vm0);
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/**
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* @brief check the iommu if support cache snoop.
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*
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* @param[in] vm pointer to VM to check
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*
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* @retval true support
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* @retval false not support
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*
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*/
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bool iommu_snoop_supported(struct acrn_vm *vm);
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/**
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* @}
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*/
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#endif
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