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ac1c79641e9b8f2b87c5d5aad9268f9fdcde58a7
acrn-hypervisor/hypervisor/include/arch/riscv/asm
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Shiqing Gao 9d95a6adb6 hv: riscv: fix stack allocation in cpu_ctx_save/cpu_ctx_restore 
The RISC-V calling convention defines a full descending stack, where 'sp'
points to the last used stack address. The current implementation of
cpu_ctx_save() subtracts only CPU_REGS_OFFSET_SCRATCH from 'sp', which
allocates 8 bytes too few and may overwrite the caller's stack contents.

Fix this by adjusting CPU_REGS_OFFSET_LAST to include the last slot,
ensuring the full context save/restore area is properly reserved.

Fixes: 6276763cd (hv: riscv: implement cpu_ctx_save and cpu_ctx_restore)

Tracked-On: #8827
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-10-14 09:45:17 +08:00
..
guest
hv: add dummy function for riscv support
2025-09-30 12:31:07 +08:00
lib
hv: multi-arch add RISC-V bits library implementation
2025-09-22 10:52:06 +08:00
cpu.h
hv: risc-v: use tp register directly for arch_get_pcpu_id
2025-10-10 17:14:22 +08:00
init.h
hv: risc-v: add C entry function of BSP and APs
2025-09-15 13:12:21 +08:00
io.h
io: add risc-v mmio read and write APIs with memory order
2025-10-09 17:15:06 +08:00
irq.h
hv: riscv: irq: add interrupt initialization and handlers
2025-09-29 14:01:00 +08:00
notify.h
hv: smpcall: riscv: implement SMP call handlers
2025-09-09 16:37:04 +08:00
offset.h
hv: riscv: fix stack allocation in cpu_ctx_save/cpu_ctx_restore
2025-10-14 09:45:17 +08:00
page.h
enable common code compile
2025-09-19 15:04:55 +08:00
per_cpu.h
hv: riscv: add get/set_pcpu_id and start_pcpus implementation
2025-09-23 11:30:38 +08:00
pgtable.h
[FIXME] hv: riscv: add build dependencies temporarily
2025-09-23 11:30:38 +08:00
qemu.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
sbi.h
hv: riscv: add SBI HSM HART_START interface
2025-09-23 11:30:38 +08:00
security.h
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00
timer.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
trap.h
hv: riscv: irq: add interrupt initialization and handlers
2025-09-29 14:01:00 +08:00
vm_config.h
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00