mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-09 00:46:57 +00:00
4d13ad9d08
- enable NX feature in hypervisor:
1. Set 'XD' bit for all pages, including pages for guests
when initialize MMU tables in hypervisor.
2. remove 'XD' bit for pages that contain hypervisor instructions.
3. enable MSR EFER.NXE,which will enable page access restriction by
preventing instruction fetches form pages with XD bit set.
- remove "-Wl -z noexecstack" GCC flag option in hypervisor
Makefile as it would not affect stack attribute in hyervisor,
which setup stack itself, instead of by loader.
Tracked-On: #1122
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
95 lines
1.6 KiB
Plaintext
95 lines
1.6 KiB
Plaintext
ENTRY(cpu_primary_start_32)
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MEMORY
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{
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/* Low 1MB of memory for secondary processor start-up */
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lowram : ORIGIN = 0, LENGTH = CONFIG_LOW_RAM_SIZE
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/* 32 MBytes of RAM for HV */
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ram : ORIGIN = CONFIG_HV_RAM_START, LENGTH = CONFIG_HV_RAM_SIZE
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}
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SECTIONS
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{
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.boot :
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{
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_ld_ram_start = . ;
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KEEP(*(multiboot_header)) ;
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} > ram
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.entry :
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{
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KEEP(*(entry)) ;
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} > ram
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.text :
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{
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*(.text .text*) ;
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*(.gnu.linkonce.t*)
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*(.note.gnu.build-id)
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*(.retpoline_thunk)
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} > ram
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/*Align text top boundary to 2MBytes.*/
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. = ALIGN(0x200000);
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ld_text_end = . ;
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.rodata :
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{
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*(.rodata*) ;
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} > ram
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.rela :
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{
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*(.rela*)
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*(.dyn*)
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} > ram
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. = ALIGN(4) ;
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ld_trampoline_load = .;
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.trampoline : AT (ld_trampoline_load)
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{
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ld_trampoline_start = .;
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*(.trampoline_reset);
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. = ALIGN(4);
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ld_trampoline_end = .;
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} > lowram
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ld_trampoline_size = ld_trampoline_end - ld_trampoline_start;
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.data (ld_trampoline_load + ld_trampoline_size):
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{
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*(.data) ;
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*(.data*) ;
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*(.sdata)
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*(.gnu.linkonce.d*)
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} > ram
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.bss_noinit (NOLOAD):
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{
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. = ALIGN(4) ;
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*(.bss_noinit) ;
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*(.bss_noinit*) ;
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. = ALIGN(4) ;
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} > ram
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.bss (NOLOAD):
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{
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. = ALIGN(4) ;
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ld_bss_start = . ;
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*(.bss) ;
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*(.bss*) ;
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*(COMMON) ;
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. = ALIGN(4) ;
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ld_bss_end = . ;
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} > ram
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_ld_ram_size = LENGTH(ram) ;
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_ld_ram_end = _ld_ram_size + _ld_ram_start ;
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}
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