Shuo Liu aed75145c1 dm: Limit 64 bits PCI BAR region address space ...

Limit 64 bits PCI BAR space from 0x100000000UL ~ 0x140000000UL,
as HV now only support 0x400000000UL+0x80000000 as top of guest memory
address. EPT table size is static allocated.

Tracked-On: #2577
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>

2019-02-28 18:33:11 +08:00

..

pci

dm: Limit 64 bits PCI BAR region address space

2019-02-28 18:33:11 +08:00

platform

DM: Attestation Keybox support in SOS DM

2019-02-25 16:40:25 +08:00

block_if.c

dm: storage: change DISCARD to synchronous mode

2019-01-23 12:56:47 +08:00

uart_core.c

dm: Add teardown callback for mevent in uart_core

2018-12-27 09:58:20 +08:00

usb_core.c

DM USB: add usb_dev_path_cmp function for convenience

2018-12-14 19:40:44 +08:00