mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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d0eb83aa0c
Previously I/O emulation completion mode mode was configured in Kconfig:
config IOREQ_NOTIFICATION
bool "Notification mode"
help
When I/O request is completed, SOS will mark the completion status and
notify hypervisor via hypercall. Hypervisor will finish the post work
when notification is received.
config IOREQ_POLLING
bool "Polling mode"
help
When I/O request is completed, SOS will only mark completion status
without notifying hypervisor. Hypervisor will poll the completion
status and finish the post work.
Now move this configuration to guest_flags of acrn_vm_config struct.
if ((vm_config->guest_flags & IO_COMPLETION_POLLING) != 0U) {
I/O with polling;
} else {
I/O with notification;
}
Tracked-On: #2291
Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
221 lines
4.6 KiB
C
221 lines
4.6 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#include <e820.h>
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static struct vpci_vdev_array vpci_vdev_array1 = {
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.num_pci_vdev = 2,
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.vpci_vdev_list = {
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{/*vdev 0: hostbridge */
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.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
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.ops = &pci_ops_vdev_hostbridge,
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.bar = {},
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.pdev = {
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.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
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}
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},
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{/*vdev 1: SATA controller*/
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.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
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.ops = &pci_ops_vdev_pt,
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.bar = {
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[0] = {
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.base = 0UL,
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.size = 0x2000UL,
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.type = PCIBAR_MEM32
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},
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[1] = {
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.base = 0UL,
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.size = 0x1000UL,
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.type = PCIBAR_MEM32
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},
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[5] = {
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.base = 0UL,
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.size = 0x1000UL,
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.type = PCIBAR_MEM32
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},
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},
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.pdev = {
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.bdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x0U},
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.bar = {
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[0] = {
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.base = 0xb3f10000UL,
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.size = 0x2000UL,
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.type = PCIBAR_MEM32
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},
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[1] = {
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.base = 0xb3f53000UL,
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.size = 0x100UL,
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.type = PCIBAR_MEM32
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},
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[5] = {
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.base = 0xb3f52000UL,
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.size = 0x800UL,
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.type = PCIBAR_MEM32
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},
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}
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}
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},
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}
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};
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static struct vpci_vdev_array vpci_vdev_array2 = {
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.num_pci_vdev = 3,
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.vpci_vdev_list = {
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{/*vdev 0: hostbridge*/
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.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
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.ops = &pci_ops_vdev_hostbridge,
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.bar = {},
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.pdev = {
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.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
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}
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},
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{/*vdev 1: USB controller*/
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.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
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.ops = &pci_ops_vdev_pt,
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.bar = {
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[0] = {
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.base = 0UL,
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.size = 0x10000UL,
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.type = PCIBAR_MEM32
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},
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},
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.pdev = {
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.bdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x0U},
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.bar = {
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[0] = {
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.base = 0xb3f00000UL,
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.size = 0x10000UL,
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.type = PCIBAR_MEM64
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},
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}
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}
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},
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{/*vdev 2: Ethernet*/
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.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x0U},
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.ops = &pci_ops_vdev_pt,
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.bar = {
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[0] = {
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.base = 0UL,
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.size = 0x80000UL,
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.type = PCIBAR_MEM32
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},
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[3] = {
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.base = 0UL,
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.size = 0x4000UL,
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.type = PCIBAR_MEM32
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},
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},
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.pdev = {
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.bdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x0U},
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.bar = {
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[0] = {
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.base = 0xb3c00000UL,
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.size = 0x80000UL,
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.type = PCIBAR_MEM32
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},
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[3] = {
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.base = 0xb3c80000UL,
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.size = 0x4000UL,
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.type = PCIBAR_MEM32
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},
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}
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}
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},
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}
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};
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/*******************************/
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/* User Defined VM definitions */
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/*******************************/
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struct vm_config_arraies vm_config_partition = {
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/* Virtual Machine descriptions */
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.vm_config_array = {
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{
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.type = PRE_LAUNCHED_VM,
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.pcpu_bitmap = (PLUG_CPU(0) | PLUG_CPU(2)),
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.guest_flags = IO_COMPLETION_POLLING,
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.memory.start_hpa = 0x100000000UL,
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.memory.size = 0x20000000UL, /* uses contiguous memory from host */
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.vm_vuart = true,
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.os_config.bootargs = "root=/dev/sda3 rw rootwait noxsave maxcpus=2 nohpet console=hvc0 \
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console=ttyS2 no_timer_check ignore_loglevel log_buf_len=16M \
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consoleblank=0 tsc=reliable xapic_phys",
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.vpci_vdev_array = &vpci_vdev_array1,
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},
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{
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.type = PRE_LAUNCHED_VM,
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.pcpu_bitmap = (PLUG_CPU(1) | PLUG_CPU(3)),
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.guest_flags = LAPIC_PASSTHROUGH | IO_COMPLETION_POLLING,
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.memory.start_hpa = 0x120000000UL,
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.memory.size = 0x20000000UL, /* uses contiguous memory from host */
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.vm_vuart = true,
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.os_config.bootargs = "root=/dev/sda3 rw rootwait noxsave maxcpus=2 nohpet console=hvc0 \
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console=ttyS2 no_timer_check ignore_loglevel log_buf_len=16M \
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consoleblank=0 tsc=reliable xapic_phys",
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.vpci_vdev_array = &vpci_vdev_array2,
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},
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}
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};
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const struct pcpu_vm_config_mapping pcpu_vm_config_map[] = {
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{
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.vm_config_ptr = &vm_config_partition.vm_config_array[0],
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.is_bsp = true,
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},
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{
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.vm_config_ptr = &vm_config_partition.vm_config_array[1],
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.is_bsp = false,
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},
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{
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.vm_config_ptr = &vm_config_partition.vm_config_array[0],
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.is_bsp = false,
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},
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{
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.vm_config_ptr = &vm_config_partition.vm_config_array[1],
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.is_bsp = true,
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},
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};
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const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
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{ /* 0 to mptable */
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.baseaddr = 0x0U,
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.length = 0xEFFFFU,
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.type = E820_TYPE_RAM
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},
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{ /* mptable 65536U */
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.baseaddr = 0xF0000U,
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.length = 0x10000U,
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.type = E820_TYPE_RESERVED
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},
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{ /* mptable to lowmem */
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.baseaddr = 0x100000U,
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.length = 0x1FF00000U,
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.type = E820_TYPE_RAM
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},
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{ /* lowmem to PCI hole */
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.baseaddr = 0x20000000U,
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.length = 0xa0000000U,
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.type = E820_TYPE_RESERVED
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},
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{ /* PCI hole to 4G */
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.baseaddr = 0xe0000000U,
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.length = 0x20000000U,
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.type = E820_TYPE_RESERVED
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},
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};
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