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https://github.com/projectacrn/acrn-hypervisor.git
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b0a4c2d024
This patch provides dummy implementations of functions and data
structures required for the IPI and SMP call on RISC-V.
It serves as a placeholder to ensure RISC-V builds pass and
is not needed for the final merge.
Official implementations are still WIP by other engineers:
- To be provided in the library patchset (by Haoyu):
uint16_t ffs64(uint64_t value);
bool bitmap_test(uint16_t nr, const volatile uint64_t *addr);
void bitmap_clear_lock(uint16_t nr_arg, volatile uint64_t *addr);
void bitmap_clear_nolock(uint16_t nr_arg, volatile uint64_t *addr);
uint64_t atomic_cmpxchg64(volatile uint64_t *ptr, uint64_t old, uint64_t new);
- To be provided in the platform initialization patchset (by Hang):
void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
bool is_pcpu_active(uint16_t pcpu_id);
uint16_t get_pcpu_id(void);
----------
Changelog:
* Split per_cpu.h implementation into a separate commit.
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
23 lines
448 B
C
23 lines
448 B
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef RISCV_ATOMIC_H
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#define RISCV_ATOMIC_H
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#include <types.h>
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static inline uint64_t atomic_cmpxchg64(__unused volatile uint64_t *ptr, __unused uint64_t old, __unused uint64_t new)
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{
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/**
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* Dummy implementation.
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* Official implementations are to be provided in the library patchset (by Haoyu).
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*/
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return 0UL;
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}
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#endif /* RISCV_ATOMIC_H */
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