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0d630e8f37
This patch implements the IPI for RISC-V using SBI interface.
There is no common IPI concept abstracted, due to the following reasons:
- RISC-V:
Software delivers an IPI to target CPUs via software interrupts.
The interrupt number is fixed for each privilege mode (e.g.,
Supervisor Software Interrupt = IRQ 1, Machine Software Interrupt = IRQ 3).
The actual purpose of the IPI is indicated by an IPI message type,
which is a software-level concept. When the IPI is received,
the target CPU must check the message type to determine the required action.
- x86:
Software delivers an IPI to target CPUs using a specific vector number.
During CPU initialization, software can assign dedicated vectors for
particular purposes. When the IPI is received, the target CPU could
directly invoke the handler bound to that vector.
Each architecture provides its own IPI implementation, and other SW modules
directly call these arch-specific functions.
------
Notes:
* To ensure RISC-V builds pass, an empty `include/arch/riscv/asm/cpu.h`
is added since `debug/logmsg.h` includes `asm/cpu.h`.
* Implemented IPI functionality using the SBI IPI Extension (EID #0x735049).
Legacy SBI extensions are not supported in ACRN.
----------
Changelog:
* Updated commit message and code comments to state explicitly that
legacy SBI extensions are not supported in ACRN.
* Refined the prototype of sbi_send_ipi() to align with the SBI spec:
From: int64_t sbi_send_ipi(uint64_t mask)
To: int64_t sbi_send_ipi(uint64_t mask, uint64_t mask_base)
In ACRN it is invoked as sbi_send_ipi(dest_mask, 0UL), with mask_base
set to 0UL.
* Renamed send_single_ipi() and send_dest_ipi_mask() to
arch_send_single_ipi() and arch_send_dest_ipi_mask() respectively.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/*
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* Copyright (C) 2023-2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#ifndef RISCV_SBI_H
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#define RISCV_SBI_H
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#include <types.h>
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enum sbi_eid {
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SBI_EID_BASE = 0x10,
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SBI_EID_TIMER = 0x54494D45,
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SBI_EID_IPI = 0x735049,
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SBI_EID_RFENCE = 0x52464E43,
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SBI_EID_HSM = 0x48534D,
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SBI_EID_SRST = 0x53525354,
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SBI_EID_PMU = 0x504D55,
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SBI_EID_MPXY = 0x4D505859,
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/* Experimental extensions must lie within this range */
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SBI_EID_EXPER_START = 0x08000000,
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SBI_EID_EXPER_END = 0x08FFFFFF,
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/* Vendor extensions must lie within this range */
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SBI_EID_VENDOR_START = 0x09000000,
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SBI_EID_VENDOR_END = 0x09FFFFFF,
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};
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#define SBI_BASE_FID_GET_SPEC_VERSION 0x0
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#define SBI_BASE_FID_GET_IMP_ID 0x1
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#define SBI_BASE_FID_GET_IMP_VERSION 0x2
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#define SBI_BASE_FID_PROBE_EXT 0x3
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#define SBI_BASE_FID_GET_MVENDORID 0x4
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#define SBI_BASE_FID_GET_MARCHID 0x5
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#define SBI_BASE_FID_GET_MIMPID 0x6
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/* SBI function IDs for TIME extension*/
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#define SBI_TIMER_FID_SET_TIMER 0x0
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/* SBI function IDs for IPI extension*/
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#define SBI_IPI_FID_SEND_IPI 0x0
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/* SBI function IDs for RFENCE extension*/
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#define SBI_RFENCE_FID_FNECE_I 0x0
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#define SBI_RFENCE_FID_SFNECE_VMA 0x1
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#define SBI_RFENCE_FID_SFNECE_VMA_ASID 0x2
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#define SBI_RFENCE_FID_HFNECE_GVMA 0x3
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#define SBI_RFENCE_FID_HFNECE_GVMA_ASID 0x4
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#define SBI_RFENCE_FID_HFNECE_VVMA 0x5
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#define SBI_RFENCE_FID_HFNECE_VVMA_ASID 0x6
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/* SBI function IDs for HSM extension*/
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#define SBI_HSM_FID_HART_START 0x0
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#define SBI_HSM_FID_HART_STOP 0x1
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#define SBI_HSM_FID_HART_GET_STATUS 0x2
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#define SBI_HSM_FID_HART_SUSPEND 0x3
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/* SBI function IDs for MPXY extension*/
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#define SBI_MPXY_FID_GET_SHM_SIZE 0x0
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#define SBI_MPXY_FID_SET_SHM 0x1
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#define SBI_MPXY_FID_GET_CHANNEL_IDS 0x2
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#define SBI_MPXY_FID_READ_ATTRS 0x3
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#define SBI_MPXY_FID_WRITE_ATTRS 0x4
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#define SBI_MPXY_FID_SEND_MSG_WITH_RESP 0x5
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#define SBI_MPXY_FID_SEND_MSG_WITHOUT_RESP 0x6
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#define SBI_MPXY_FID_GET_NOTFICATION_EVENTS 0x7
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/* SBI return error codes */
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#define SBI_SUCCESS 0
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#define SBI_ERR_FAILED -1
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#define SBI_ERR_NOT_SUPPORTED -2
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#define SBI_ERR_INVALID_PARAM -3
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#define SBI_ERR_DENIED -4
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#define SBI_ERR_INVALID_ADDRESS -5
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#define SBI_ERR_ALREADY_AVAILABLE -6
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#define SBI_ERR_ALREADY_STARTED -7
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#define SBI_ERR_ALREADY_STOPPED -8
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#define SBI_ERR_NO_SHMEM -9
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#define SBI_ERR_INVALID_STATE -10
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#define SBI_ERR_BAD_RANGE -11
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#define SBI_ERR_TIMEOUT -12
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#define SBI_ERR_IO -13
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#define SBI_ERR_DENIED_LOCKED -14
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#define SBI_RFENCE_FLUSH_ALL ((uint64_t)-1)
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typedef struct {
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int64_t error;
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union {
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int64_t value;
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uint64_t uvalue;
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};
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} sbiret;
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void arch_send_single_ipi(uint16_t pcpu_id, __unused uint32_t msg_type);
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void arch_send_dest_ipi_mask(uint64_t dest_mask, __unused uint32_t msg_type);
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#endif /* RISCV_SBI_H */
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