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3834f6ac96
Issue description: ----------------- Machine Check Error on Page Size Change Instruction fetch may cause machine check error if page size and memory type was changed without invalidation on some processors[1][2]. Malicious guest kernel could trigger this issue. This issue applies to both primary page table and extended page tables (EPT), however the primary page table is controlled by hypervisor only. This patch mitigates the situation in EPT. Mitigation details: ------------------ Implement non-execute huge pages in EPT. This patch series clears the execute permission (bit 2) in the EPT entries for large pages. When EPT violation is triggered by guest instruction fetch, hypervisor converts the large page to smaller 4 KB pages and restore the execute permission, and then re-execute the guest instruction. The current patch turns on the mitigation by default. The follow-up patches will conditionally turn on/off the feature per processor model. [1] Refer to erratum KBL002 in "7th Generation Intel Processor Family and 8th Generation Intel Processor Family for U Quad Core Platforms Specification Update" https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/7th-gen-core-family-spec-update.pdf [2] Refer to erratum SKL002 in "6th Generation Intel Processor Family Specification Update" https://www.intel.com/content/www/us/en/products/docs/processors/core/desktop-6th-gen-core-family-spec-update.html Tracked-On: #4121 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com>
84 lines
2.7 KiB
C
84 lines
2.7 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PAGE_H
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#define PAGE_H
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#define PAGE_SHIFT 12U
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#define PAGE_SIZE (1U << PAGE_SHIFT)
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#define PAGE_MASK 0xFFFFFFFFFFFFF000UL
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/* size of the low MMIO address space: 2GB */
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#define PLATFORM_LO_MMIO_SIZE 0x80000000UL
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/* size of the high MMIO address space: 1GB */
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#define PLATFORM_HI_MMIO_SIZE 0x40000000UL
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#define PML4_PAGE_NUM(size) 1UL
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#define PDPT_PAGE_NUM(size) (((size) + PML4E_SIZE - 1UL) >> PML4E_SHIFT)
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#define PD_PAGE_NUM(size) (((size) + PDPTE_SIZE - 1UL) >> PDPTE_SHIFT)
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#define PT_PAGE_NUM(size) (((size) + PDE_SIZE - 1UL) >> PDE_SHIFT)
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/*
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* The size of the guest physical address space, covered by the EPT page table of a VM.
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* With the assumptions:
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* - The GPA of DRAM & MMIO are contiguous.
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* - Guest OS won't re-program device MMIO bars to the address not covered by
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* this EPT_ADDRESS_SPACE.
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*/
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#define EPT_ADDRESS_SPACE(size) (((size) != 0UL) ? ((size) + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE) : 0UL)
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#define TRUSTY_PML4_PAGE_NUM(size) (1UL)
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#define TRUSTY_PDPT_PAGE_NUM(size) (1UL)
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#define TRUSTY_PD_PAGE_NUM(size) (PD_PAGE_NUM(size))
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#define TRUSTY_PT_PAGE_NUM(size) (PT_PAGE_NUM(size))
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#define TRUSTY_PGTABLE_PAGE_NUM(size) \
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(TRUSTY_PML4_PAGE_NUM(size) + TRUSTY_PDPT_PAGE_NUM(size) + TRUSTY_PD_PAGE_NUM(size) + TRUSTY_PT_PAGE_NUM(size))
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struct acrn_vm;
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struct page {
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uint8_t contents[PAGE_SIZE];
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} __aligned(PAGE_SIZE);
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union pgtable_pages_info {
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struct {
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struct page *pml4_base;
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struct page *pdpt_base;
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struct page *pd_base;
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struct page *pt_base;
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} ppt;
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struct {
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uint64_t top_address_space;
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struct page *nworld_pml4_base;
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struct page *nworld_pdpt_base;
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struct page *nworld_pd_base;
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struct page *nworld_pt_base;
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struct page *sworld_pgtable_base;
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struct page *sworld_memory_base;
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} ept;
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};
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struct memory_ops {
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union pgtable_pages_info *info;
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uint64_t (*get_default_access_right)(void);
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uint64_t (*pgentry_present)(uint64_t pte);
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struct page *(*get_pml4_page)(const union pgtable_pages_info *info);
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struct page *(*get_pdpt_page)(const union pgtable_pages_info *info, uint64_t gpa);
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struct page *(*get_pd_page)(const union pgtable_pages_info *info, uint64_t gpa);
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struct page *(*get_pt_page)(const union pgtable_pages_info *info, uint64_t gpa);
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void *(*get_sworld_memory_base)(const union pgtable_pages_info *info);
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void (*clflush_pagewalk)(const void *p);
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void (*tweak_exe_right)(uint64_t *entry);
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void (*recover_exe_right)(uint64_t *entry);
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};
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extern const struct memory_ops ppt_mem_ops;
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void init_ept_mem_ops(struct memory_ops *mem_ops, uint16_t vm_id);
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void *get_reserve_sworld_memory_base(void);
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#endif /* PAGE_H */
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