Jian Jun Chen b25a30f271 dm: add default handling in pci_emul_capwrite ...

Virtio 1.0 introduced several PCIY_VENDOR capabilities. When trying to
write to these capabilities no action is taken so the registers in
the capability of VIRTIO_PCI_CAP_PCI_CFG such as bar, offset and length
remain the default value 0. Later a read or write of pci_cfg_data needs
these information to perform the indirect read or write to the bar
region.

Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

2018-05-31 11:25:15 +08:00

..

virtio

DM: Refactor RPMB files

2018-05-30 13:51:03 +08:00

ahci.c

DM: fix build issue with gcc 4.8.4 on ubuntu 14.04

2018-05-15 17:25:26 +08:00

core.c

dm: add default handling in pci_emul_capwrite

2018-05-31 11:25:15 +08:00

gvt.c

DM/GVT: implement emulated graphics pci device

2018-05-23 13:11:28 +08:00

hostbridge.c

initial import

2018-05-11 14:44:28 +08:00

irq.c

Enable FORTIFY and FORMAT SECURITY compile flags

2018-05-15 17:19:37 +08:00

lpc.c

DM: lpc_deinit doesn't release all resources allocated.

2018-05-15 17:25:55 +08:00

passthrough.c

DM: Add option of no check against ptdev reset

2018-05-29 13:44:13 +08:00

uart.c

DM: cleanup resource for uart.

2018-05-15 17:25:55 +08:00

wdt_i6300esb.c

delete watchdog timer when deinit is called

2018-05-15 17:25:55 +08:00

xhci.c

DM USB: xHCI: add log level switch

2018-05-29 10:35:05 +08:00