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090aaf4c34
Follow multi-arch design, implement the mandatory arch barrier functions declared in common barrier.h for risc-v support. Tracked-On: #8803 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Co-developed-by: Haoyu Tang <haoyu.tang@intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
63 lines
2.5 KiB
C
63 lines
2.5 KiB
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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#include <types.h>
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#include <lib/util.h>
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#include <debug/logmsg.h>
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#include <board_info.h>
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#include <barrier.h>
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#define cpu_relax() cpu_memory_barrier() /* TODO: replace with yield instruction */
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#define NR_CPUS MAX_PCPU_NUM
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#define LONG_BYTEORDER 3
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#define BYTES_PER_LONG (1 << LONG_BYTEORDER)
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#define BITS_PER_LONG (BYTES_PER_LONG << 3)
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/* Define the interrupt enable bit mask */
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#define SSTATUS_SIE 0x2
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static inline uint16_t get_pcpu_id(void)
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{
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/**
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* Dummy implementation.
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* Official implementations are to be provided in the platform initialization patchset (by Hang).
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*/
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return 0U;
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}
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/* Write CSR */
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#define cpu_csr_write(reg, csr_val) \
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({ \
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uint64_t val = (uint64_t)csr_val; \
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asm volatile(" csrw " STRINGIFY(reg) ", %0 \n\t" ::"r"(val) : "memory"); \
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})
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/**
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* FIXME: to follow multi-arch design, refactor all of them into static inline functions with corresponding
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* X86 implementation together.
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*/
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#define local_irq_disable() asm volatile("csrc sstatus, %0\n" ::"i"(SSTATUS_SIE) : "memory")
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#define local_irq_enable() asm volatile("csrs sstatus, %0\n" ::"i"(SSTATUS_SIE) : "memory")
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#define local_save_flags(x) ({ asm volatile("csrr %0, sstatus, 0\n" : "=r"(x)::"memory"); })
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#define local_irq_restore(x) ({ asm volatile("csrs sstatus, %0\n" ::"rK"(x & SSTATUS_SIE) : "memory"); })
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#define local_irq_save(x) \
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({ \
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uint32_t val = 0U; \
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asm volatile("csrrc %0, sstatus, 0\n" : "=r"(val) : "i"(SSTATUS_SIE) : "memory"); \
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*(uint32_t *)(x) = val; \
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})
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#define CPU_INT_ALL_DISABLE(x) local_irq_save(x)
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#define CPU_INT_ALL_RESTORE(x) local_irq_restore(x)
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void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
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#endif /* RISCV_CPU_H */
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