Chenli Wei 4807385fe2 misc: refine cache config ...

The current RDT setting requires users to calculate the CLOS mask and
the details, it is not a user-friendly setting.

So we redesigned RDT, users can easily specify the cache of each vcpu
for VMs.

This patch add an RDT region element for schema, calculate and generate
all the mask and rdt parameters by config tool to generates rdt_info
struct for board.c.

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>

2022-04-24 16:52:24 +08:00

..

lib

Remove "All rights reserved" string headers

2022-04-06 13:21:02 +08:00

bdf.py

misc: refine vuart connection

2022-03-08 17:07:48 +08:00

board_capability.py

config-tools: generate ACFG_MAX_PCI_BUS_NUM based on board.xml

2021-12-13 11:06:10 +08:00

clos.py

misc: refine cache config

2022-04-24 16:52:24 +08:00

cpu_affinity.py

config_tools: track whether each vCPU is used for real-time or not

2022-04-21 10:08:53 +08:00

gpa.py

config-tools: extract the SSRAM area size

2022-04-18 16:47:23 +08:00

guest_flags.py

misc: set PMU_PT flag for pre-launched RTVM

2022-03-29 09:34:17 +08:00

intx.py

Remove "All rights reserved" string headers

2022-04-06 13:21:02 +08:00

main.py

Remove "All rights reserved" string headers

2022-04-06 13:21:02 +08:00

memory_allocator.py

misc: alloc HPAn by VM whole size setting

2022-04-22 14:46:05 +08:00

pio.py

Remove "All rights reserved" string headers

2022-04-06 13:21:02 +08:00