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https://github.com/projectacrn/acrn-hypervisor.git
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6f97ad9fc9
The following tasks are done for both BSP and APs: - Mask all interrupts - Disable FPU - Setup stack - Jump to the C entry of BSP/AP initialization Additionally, clear BSS sections during BSP boot before jumping to the C entry point. Tracked-On: #8788 Signed-off-by: Haicheng Li <haicheng.li@intel.com> Co-developed-by: Haicheng Li <haicheng.li@intel.com> Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
68 lines
1.1 KiB
ArmAsm
68 lines
1.1 KiB
ArmAsm
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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.section .text.entry, "ax", %progbits
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/*
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* main entry point
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* - a0 = hart ID
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* - a1 = dtb address
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*/
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.globl _start
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_start:
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/* Mask all interrupts */
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csrw sie, zero
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/* Disable FPU bit[14:13] */
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li t0, 0x00006000
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csrc sstatus, t0
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/* Set trap vector to spin forever for debug */
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lla a3, _start_hang
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csrw stvec, a3
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/* Clear BSS */
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lla t3, _bss_start
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lla t4, _bss_end
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_clear_bss:
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sd zero, (t3)
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add t3, t3, __SIZEOF_POINTER__
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bltu t3, t4, _clear_bss
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/* Setup cpu0 boot stack (full descending) */
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lla sp, _boot_stack_end
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/* a0 = hart_id, a1 = dtb_address */
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tail init_primary_pcpu
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.align 2
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.global _start_secondary_sbi
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_start_secondary_sbi:
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/* Mask all interrupts */
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csrw sie, zero
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/* Disable FPU bit[14:13] */
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li t0, 0x00006000
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csrc sstatus, t0
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/* Set trap vector to spin forever for debug */
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lla a3, _start_hang
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csrw stvec, a3
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/* a0 contains the hartid & a1 contains stack physical addr */
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mv sp, a1
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tail init_secondary_pcpu
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.align 2
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_start_hang:
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wfi
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j _start_hang
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