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https://github.com/projectacrn/acrn-hypervisor.git
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fc495b946a
This patch implements interrupt initialization and the basic exception/interrupt handling flow on RISC-V. init_interrupt() needs to be invoked during CPU initialization to set up the trap vector and enable the interrupt. RISC-V exception and interrupt handling includes: - Saving and restoring CPU registers around traps - Implementing handlers for: - Supervisor software interrupt - Supervisor timer interrupt - Halting the CPU for all other interrupts and exceptions ------ TODOs: 1. add support for registering interrupt handlers via request_irq() and further adoption of the common IRQ framework. 2. add support for external interrupt. Tracked-On: #8813 Signed-off-by: Haicheng Li <haicheng.li@intel.com> Co-developed-by: Shiqing Gao <shiqing.gao@intel.com> Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
28 lines
558 B
ArmAsm
28 lines
558 B
ArmAsm
/*
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* Copyright (C) 2023-2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#include <asm/trap.h>
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#include <cpu.h>
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.text
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.balign 4
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.globl strap_handler
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strap_handler:
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/** Save CPU registers (`struct cpu_regs` within `struct intr_excp_ctx`) to stack. */
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cpu_ctx_save
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/** Pass sp in a0, as the argument to dispatch_trap(). */
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mv a0, sp
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call dispatch_trap
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/** Restore CPU registers (`struct cpu_regs` within `struct intr_excp_ctx`) from stack. */
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cpu_ctx_restore
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sret
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