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ca778139e6
Convert IRQ-related macros to static inline functions and introduce
wrappers for arch-specific implementations. This follows the style we
defined for multi-arch development.
This is a follow-up update for commit
a7239d126 ("[FIXME] hv: risc-v add denpended implementation in cpu.h").
CPU_IRQ_ENABLE_ON_CONFIG -> local_irq_enable
CPU_IRQ_DISABLE_ON_CONFIG -> local_irq_disable
CPU_INT_ALL_DISABLE -> local_irq_save
CPU_INT_ALL_RESTORE -> local_irq_restore
Tracked-On: #8813
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
/*
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* Copyright (C) 2023-2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#include <asm/trap.h>
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#include <cpu.h>
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#include <types.h>
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static void init_interrupt_arch(__unused uint16_t pcpu_id)
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{
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uint64_t addr = (uint64_t)&strap_handler;
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/*
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* According to RISC-V Privileged Architecture
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* 12.1.2. Supervisor Trap Vector Base Address (stvec) Register:
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* The BASE field in stvec is a field that can hold any valid virtual
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* or physical address, subject to the following alignment constraints:
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* the address must be ``4-byte aligned``, and MODE settings other than
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* Direct might impose additional alignment constraints on the
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* value in the BASE field.
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*/
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cpu_csr_write(stvec, (addr | TRAP_VECTOR_MODE_DIRECT));
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cpu_csr_write(sie, (IP_IE_SSI | IP_IE_STI | IP_IE_SEI));
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}
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/*
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* TODO:
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* This is the first step toward aligning with the common IRQ framework.
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* For simplicity in this patchset, which focuses only on initialization,
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* init_interrupt() is defined directly in arch/riscv/irq.c.
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*
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* Because interrupt handler registration via request_irq() is not yet
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* implemented for RISC-V, fully aligning with the framework would require
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* adding a few empty arch-specific functions as placeholders.
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*
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* Once request_irq() support is introduced, we can complete the integration
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* with the common IRQ framework.
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*/
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void init_interrupt(uint16_t pcpu_id)
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{
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init_interrupt_arch(pcpu_id);
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local_irq_enable();
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}
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