mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-11-16 05:31:16 +00:00
f6bf0b809d
This patch implements risc-v specific timer codes. Basically, risc-v adapts to acrn timer framework with some specific behaviors. So far, it enables sstc support in h-mode. Tracked-On: #8792 Signed-off-by: Haicheng Li <haicheng.li@outlook.com> Co-developed-by: Yong Li <yong.li@intel.com> Signed-off-by: Yong Li <yong.li@intel.com> Co-developed-by: Yi Y Sun <yi.y.sun@intel.com> Signed-off-by: Yi Y Sun <yi.y.sun@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
49 lines
1.0 KiB
C
49 lines
1.0 KiB
C
/*
|
|
* Copyright (C) 2025 Intel Corporation.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*
|
|
*/
|
|
|
|
#ifndef RISCV_CPU_H
|
|
#define RISCV_CPU_H
|
|
|
|
#include <types.h>
|
|
#include <lib/util.h>
|
|
|
|
static inline void wait_sync_change(__unused volatile const uint64_t *sync, __unused uint64_t wake_sync)
|
|
{
|
|
/**
|
|
* Dummy implementation.
|
|
* Official implementations are to be provided in the platform initialization patchset (by Hang).
|
|
*/
|
|
}
|
|
|
|
static inline bool is_pcpu_active(__unused uint16_t pcpu_id)
|
|
{
|
|
/**
|
|
* Dummy implementation.
|
|
* Official implementations are to be provided in the platform initialization patchset (by Hang).
|
|
*/
|
|
return true;
|
|
}
|
|
|
|
static inline uint16_t get_pcpu_id(void)
|
|
{
|
|
/**
|
|
* Dummy implementation.
|
|
* Official implementations are to be provided in the platform initialization patchset (by Hang).
|
|
*/
|
|
return 0U;
|
|
}
|
|
|
|
/* Write CSR */
|
|
#define cpu_csr_write(reg, csr_val) \
|
|
({ \
|
|
uint64_t val = (uint64_t)csr_val; \
|
|
asm volatile (" csrw " STRINGIFY(reg) ", %0 \n\t" \
|
|
:: "r"(val): "memory"); \
|
|
})
|
|
|
|
#endif /* RISCV_CPU_H */
|