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https://github.com/projectacrn/acrn-hypervisor.git
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f6bf0b809d
This patch implements risc-v specific timer codes. Basically, risc-v adapts to acrn timer framework with some specific behaviors. So far, it enables sstc support in h-mode. Tracked-On: #8792 Signed-off-by: Haicheng Li <haicheng.li@outlook.com> Co-developed-by: Yong Li <yong.li@intel.com> Signed-off-by: Yong Li <yong.li@intel.com> Co-developed-by: Yi Y Sun <yi.y.sun@intel.com> Signed-off-by: Yi Y Sun <yi.y.sun@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
16 lines
279 B
C
16 lines
279 B
C
/*
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* Copyright (C) 2023-2024 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#ifndef __RISCV_QEMU_H__
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#define __RISCV_QEMU_H__
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#define CONFIG_SSTC 1
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#endif /* __RISCV_QEMU_H__ */
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