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without the msr.h file the build will be failed when CAT is enabled. Tracked-On: #4066 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
173 lines
6.4 KiB
Python
173 lines
6.4 KiB
Python
# Copyright (C) 2019 Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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import sys
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import board_cfg_lib
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INCLUDE_HEADER = """
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#include <board.h>
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#include <vtd.h>
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#include <msr.h>"""
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MSR_IA32_L2_MASK_BASE = 0x00000D10
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MSR_IA32_L2_MASK_END = 0x00000D4F
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MSR_IA32_L3_MASK_BASE = 0x00000C90
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MSR_IA32_L3_MASK_END = 0x00000D0F
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def gen_dmar_structure(config):
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"""Generate dmar structure information"""
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dmar_info_lines = board_cfg_lib.get_info(board_cfg_lib.BOARD_INFO_FILE, "<DRHD_INFO>", "</DRHD_INFO>")
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drhd_cnt = 0
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drhd_dev_scope_cnt = []
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dev_scope_type = []
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# parse to get DRHD count and dev scope count
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for dmar_line in dmar_info_lines:
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if "DRHD_COUNT" in dmar_line and not drhd_cnt:
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drhd_cnt = int(dmar_line.split()[2].strip('U'))
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for i_cnt in range(drhd_cnt):
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for dmar_line in dmar_info_lines:
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dev_scope_cnt_str = "DRHD{}_DEV_CNT".format(i_cnt)
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if dev_scope_cnt_str in dmar_line:
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tmp_dev_scope_cnt = int(dmar_line.split()[2].strip('U'), 16)
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drhd_dev_scope_cnt.append(tmp_dev_scope_cnt)
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# gen dmar structure information
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for i_drhd_cnt in range(drhd_cnt):
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dev_cnt = drhd_dev_scope_cnt[i_drhd_cnt]
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print("static struct dmar_dev_scope drhd{}_dev_scope[DRHD{}_DEV_CNT] = {{".format(
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i_drhd_cnt, i_drhd_cnt), file=config)
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for i_dev_cnt in range(dev_cnt):
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print("\t{", file=config)
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print("\t\t.type = DRHD{}_DEVSCOPE{}_TYPE,".format(i_drhd_cnt, i_dev_cnt), file=config)
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print("\t\t.id = DRHD{}_DEVSCOPE{}_ID,".format(i_drhd_cnt, i_dev_cnt), file=config)
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print("\t\t.bus = DRHD{}_DEVSCOPE{}_BUS,".format(i_drhd_cnt, i_dev_cnt), file=config)
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print("\t\t.devfun = DRHD{}_DEVSCOPE{}_PATH,".format(i_drhd_cnt, i_dev_cnt), file=config)
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print("\t},", file=config)
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print("};", file=config)
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print("", file=config)
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print("static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {", file=config)
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for i_drhd_cnt in range(drhd_cnt):
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print("\t{", file=config)
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print("\t\t.dev_cnt = DRHD{}_DEV_CNT,".format(i_drhd_cnt), file=config)
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print("\t\t.segment = DRHD{}_SEGMENT,".format(i_drhd_cnt), file=config)
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print("\t\t.flags = DRHD{}_FLAGS,".format(i_drhd_cnt), file=config)
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print("\t\t.reg_base_addr = DRHD{}_REG_BASE,".format(i_drhd_cnt), file=config)
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print("\t\t.ignore = DRHD{}_IGNORE,".format(i_drhd_cnt), file=config)
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print("\t\t.devices = drhd{}_dev_scope".format(i_drhd_cnt), file=config)
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print("\t},", file=config)
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print("};", file=config)
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print("", file=config)
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print("struct dmar_info plat_dmar_info = {", file=config)
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print("\t.drhd_count = DRHD_COUNT,", file=config)
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print("\t.drhd_units = drhd_info_array,", file=config)
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print("};", file=config)
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def gen_cat(config):
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"""
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Get CAT information
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:param config: it is a file pointer of board information for writing to
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"""
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err_dic = {}
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(cache_support, clos_max) = board_cfg_lib.clos_info_parser(board_cfg_lib.BOARD_INFO_FILE)
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if clos_max > MSR_IA32_L2_MASK_END - MSR_IA32_L2_MASK_BASE or\
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clos_max > MSR_IA32_L3_MASK_END - MSR_IA32_L3_MASK_BASE:
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err_dic["board config: generate board.c failed"] = "CLOS MAX should be less than reserved adress region length of L2/L3 cache"
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return err_dic
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if cache_support == "False" or clos_max == 0:
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print("\nstruct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];", file=config)
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else:
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print("\nstruct platform_clos_info platform_clos_array[{}] = {{".format(
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"MAX_PLATFORM_CLOS_NUM"), file=config)
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for i_cnt in range(clos_max):
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print("\t{", file=config)
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print("\t\t.clos_mask = {0}U,".format(hex(0xff)), file=config)
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if cache_support == "L2":
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print("\t\t.msr_index = MSR_IA32_L2_MASK_BASE + {}U,".format(i_cnt), file=config)
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elif cache_support == "L3":
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print("\t\t.msr_index = MSR_IA32_L3_MASK_BASE + {}U,".format(i_cnt), file=config)
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else:
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err_dic['board config: generate board.c failed'] = "The input of {} was corrupted!".format(board_cfg_lib.BOARD_INFO_FILE)
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return err_dic
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print("\t},", file=config)
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print("};\n", file=config)
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print("", file=config)
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return err_dic
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def gen_px_cx(config):
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"""
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Get Px/Cx and store them to board.c
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:param config: it is a file pointer of board information for writing to
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"""
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cpu_brand_lines = board_cfg_lib.get_info(
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board_cfg_lib.BOARD_INFO_FILE, "<CPU_BRAND>", "</CPU_BRAND>")
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cx_lines = board_cfg_lib.get_info(board_cfg_lib.BOARD_INFO_FILE, "<CX_INFO>", "</CX_INFO>")
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px_lines = board_cfg_lib.get_info(board_cfg_lib.BOARD_INFO_FILE, "<PX_INFO>", "</PX_INFO>")
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cx_len = len(cx_lines)
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px_len = len(px_lines)
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#print("#ifdef CONFIG_CPU_POWER_STATES_SUPPORT", file=config)
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print("static const struct cpu_cx_data board_cpu_cx[%s] = {"%str(cx_len), file=config)
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for cx_l in cx_lines:
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print("\t{0}".format(cx_l.strip()), file=config)
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print("};\n", file=config)
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print("static const struct cpu_px_data board_cpu_px[%s] = {"%str(px_len), file=config)
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for px_l in px_lines:
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print("\t{0}".format(px_l.strip()), file=config)
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print("};\n", file=config)
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for brand_line in cpu_brand_lines:
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cpu_brand = brand_line
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print("const struct cpu_state_table board_cpu_state_tbl = {", file=config)
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print("\t{0},".format(cpu_brand.strip()), file=config)
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print("\t{(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px,", file=config)
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print("\t(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}", file=config)
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print("};", file=config)
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#print("#endif", file=config)
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def generate_file(config):
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"""
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Start to generate board.c
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:param config: it is a file pointer of board information for writing to
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"""
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err_dic = {}
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print("{0}".format(board_cfg_lib.HEADER_LICENSE), file=config)
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# insert bios info into board.c
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board_cfg_lib.handle_bios_info(config)
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print(INCLUDE_HEADER, file=config)
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# start to parse DMAR info
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gen_dmar_structure(config)
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# start to parse to get CAT info
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err_dic = gen_cat(config)
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if err_dic:
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return err_dic
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# start to parse PX/CX info
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gen_px_cx(config)
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return err_dic
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