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https://github.com/projectacrn/acrn-hypervisor.git
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3027bfab10
In the hypervisor, physical cpu id is defined as "int" or "uint32_t"
type in the hypervisor. So there are some sign conversion issues
about physical cpu id (pcpu_id) reported by static analysis tool.
Sign conversion violates the rules of MISRA C:2012.
In this patch, define physical cpu id as "uint16_t" type for all
modules in the hypervisor and change related codes. The valid
range of pcpu_id is 0~65534, INVALID_PCPU_ID is defined to the
invalid pcpu_id for error detection, BROADCAST_PCPU_ID is
broadcast pcpu_id used to notify all valid pcpu.
The type of pcpu_id in the struct vcpu and vcpu_id is "int" type,
this will be fixed in another patch.
V1-->V2:
* Change the type of pcpu_id from uint32_t to uint16_t;
* Define INVALID_PCPU_ID for error detection;
* Define BROADCAST_PCPU_ID to notify all valid pcpu.
V2-->V3:
* Update comments for INVALID_PCPU_ID and BROADCAST_PCPU_ID;
* Update addtional pcpu_id;
* Convert hexadecimals to unsigned to meet the type of pcpu_id;
* Clean up for MIN_PCPU_ID and MAX_PCPU_ID, they will be
defined by configuration.
Note: fix bug in the init_lapic(), the pcpu_id shall be less than 8,
this is constraint by implement in the init_lapic().
Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
136 lines
5.0 KiB
C
136 lines
5.0 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VLAPIC_H_
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#define _VLAPIC_H_
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struct vlapic;
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/* APIC write handlers */
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void vlapic_set_cr8(struct vlapic *vlapic, uint64_t val);
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uint64_t vlapic_get_cr8(struct vlapic *vlapic);
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/*
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* Returns 0 if there is no eligible vector that can be delivered to the
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* guest at this time and non-zero otherwise.
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*
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* If an eligible vector number is found and 'vecptr' is not NULL then it will
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* be stored in the location pointed to by 'vecptr'.
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*
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* Note that the vector does not automatically transition to the ISR as a
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* result of calling this function.
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*/
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int vlapic_pending_intr(struct vlapic *vlapic, uint32_t *vecptr);
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/*
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* Transition 'vector' from IRR to ISR. This function is called with the
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* vector returned by 'vlapic_pending_intr()' when the guest is able to
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* accept this interrupt (i.e. RFLAGS.IF = 1 and no conditions exist that
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* block interrupt delivery).
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*/
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void vlapic_intr_accepted(struct vlapic *vlapic, uint32_t vector);
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struct vlapic *vm_lapic_from_vcpuid(struct vm *vm, int vcpu_id);
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struct vlapic *vm_lapic_from_pcpuid(struct vm *vm, uint16_t pcpu_id);
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bool vlapic_msr(uint32_t num);
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int vlapic_rdmsr(struct vcpu *vcpu, uint32_t msr, uint64_t *rval);
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int vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t wval);
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int vlapic_mmio_read(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval, int size);
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int vlapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size);
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/*
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* Signals to the LAPIC that an interrupt at 'vector' needs to be generated
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* to the 'cpu', the state is recorded in IRR.
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*/
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int vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool trig);
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#define LAPIC_TRIG_LEVEL true
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#define LAPIC_TRIG_EDGE false
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static inline int
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vlapic_intr_level(struct vcpu *vcpu, uint32_t vector)
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{
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return vlapic_set_intr(vcpu, vector, LAPIC_TRIG_LEVEL);
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}
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static inline int
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vlapic_intr_edge(struct vcpu *vcpu, uint32_t vector)
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{
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return vlapic_set_intr(vcpu, vector, LAPIC_TRIG_EDGE);
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}
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/*
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* Triggers the LAPIC local interrupt (LVT) 'vector' on 'cpu'. 'cpu' can
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* be set to -1 to trigger the interrupt on all CPUs.
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*/
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int vlapic_set_local_intr(struct vm *vm, int vcpu_id, uint32_t vector);
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int vlapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg);
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void vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest,
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bool phys, int delmode, int vec);
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/* Reset the trigger-mode bits for all vectors to be edge-triggered */
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void vlapic_reset_tmr(struct vlapic *vlapic);
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/*
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* Set the trigger-mode bit associated with 'vector' to level-triggered if
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* the (dest,phys,delmode) tuple resolves to an interrupt being delivered to
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* this 'vlapic'.
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*/
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void vlapic_set_tmr_one_vec(struct vlapic *vlapic, int delmode,
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uint32_t vector, bool level);
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void
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vlapic_apicv_batch_set_tmr(struct vlapic *vlapic);
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int vlapic_mmio_access_handler(struct vcpu *vcpu, struct mem_io *mmio,
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void *handler_private_data);
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uint32_t vlapic_get_id(struct vlapic *vlapic);
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uint8_t vlapic_get_apicid(struct vlapic *vlapic);
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int vlapic_create(struct vcpu *vcpu);
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void vlapic_free(struct vcpu *vcpu);
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void vlapic_init(struct vlapic *vlapic);
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void vlapic_reset(struct vlapic *vlapic);
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void vlapic_restore(struct vlapic *vlapic, struct lapic_regs *regs);
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bool vlapic_enabled(struct vlapic *vlapic);
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uint64_t apicv_get_apic_access_addr(struct vm *vm);
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uint64_t apicv_get_apic_page_addr(struct vlapic *vlapic);
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bool vlapic_apicv_enabled(struct vcpu *vcpu);
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void apicv_inject_pir(struct vlapic *vlapic);
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int apic_access_vmexit_handler(struct vcpu *vcpu);
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int apic_write_vmexit_handler(struct vcpu *vcpu);
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int veoi_vmexit_handler(struct vcpu *vcpu);
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int tpr_below_threshold_vmexit_handler(struct vcpu *vcpu);
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void calcvdest(struct vm *vm, uint64_t *dmask, uint32_t dest, bool phys);
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#endif /* _VLAPIC_H_ */
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