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https://github.com/projectacrn/acrn-hypervisor.git
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b8a021d658
Upcoming intel platforms can support both L2 and L3 but our current code only supports either L2 or L3 CAT. So split the MSRs so that we can support allocation for both L2 and L3. This patch does the following, 1. splits programming of L2 and L3 cache resource based on the resource ID. 2. Replace generic platform_clos_array struct with resource specific struct in all the existing board.c files. Tracked-On: #3715 Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
32 lines
776 B
C
32 lines
776 B
C
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include <types.h>
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#include <misc_cfg.h>
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#include <host_pm.h>
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#include <pci.h>
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/* forward declarations */
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struct acrn_vm;
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struct platform_clos_info {
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uint32_t clos_mask;
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uint32_t msr_index;
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};
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extern struct dmar_info plat_dmar_info;
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extern struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
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extern struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
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extern const struct cpu_state_table board_cpu_state_tbl;
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extern const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
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/* board specific functions */
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void create_prelaunched_vm_e820(struct acrn_vm *vm);
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#endif /* BOARD_H */
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