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b6854ac4bd
MMIO read/write without memory order should be common ARCH, without PIO support shouldn't use PIO APIs, so implement them as empty. Tracked-On: #8807 Signed-off-by: Fei Li <fei1.li@intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
/*
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* Copyright (C) 2018-2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef X86_IO_H
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#define X86_IO_H
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#include <types.h>
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#define HAS_ARCH_PIO
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/* X86 architecture only supports 16 bits IO space */
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#define IO_SPACE_BITMASK 0xffffU
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/* Write 1 byte to specified I/O port */
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static inline void arch_pio_write8(uint8_t value, uint16_t port)
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{
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asm volatile ("outb %0,%1"::"a" (value), "dN"(port));
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}
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/* Read 1 byte from specified I/O port */
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static inline uint8_t arch_pio_read8(uint16_t port)
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{
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uint8_t value;
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asm volatile ("inb %1,%0":"=a" (value):"dN"(port));
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return value;
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}
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/* Write 2 bytes to specified I/O port */
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static inline void arch_pio_write16(uint16_t value, uint16_t port)
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{
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asm volatile ("outw %0,%1"::"a" (value), "dN"(port));
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}
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/* Read 2 bytes from specified I/O port */
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static inline uint16_t arch_pio_read16(uint16_t port)
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{
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uint16_t value;
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asm volatile ("inw %1,%0":"=a" (value):"dN"(port));
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return value;
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}
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/* Write 4 bytes to specified I/O port */
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static inline void arch_pio_write32(uint32_t value, uint16_t port)
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{
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asm volatile ("outl %0,%1"::"a" (value), "dN"(port));
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}
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/* Read 4 bytes from specified I/O port */
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static inline uint32_t arch_pio_read32(uint16_t port)
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{
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uint32_t value;
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asm volatile ("inl %1,%0":"=a" (value):"dN"(port));
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return value;
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}
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#endif /* X86_IO_H defined */
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